Abstract: The integrated circuit (IC) described herein lowers the start-up voltage to, for example, 50 mV, compatible for starting a DC-DC converter from a thermoelectric generator (TEG), even with a small temperature gradient. The IC further improves end-to-end efficiency of the energy harvester by improving power efficiency of the DC-DC converter while ensuring maximum power transfer from the TEG at low voltages. The IC uses a low voltage integrated charge pump that can boost sub-100 mV input voltage. A startup clock is generated by a ring-oscillator that begins operation with low supply (e.g., 50 mV or less), and which allows for one inductor to be used for DC-DC converter and for startup of the converter. The IC can be configured between the TEG and any downstream sensor or communication circuits to provide an acceptable (e.g., greater than 1 V) voltage for powering the downstream circuits from a low-voltage (e.g., less than 200 mV) TEG energy source.

Abstract: A battery-less heartbeat monitoring system that operates continuously using energy harvested from a low-grade heat source or small thermal gradient, such as human body heat and the gradient that exists between skin and the ambient environment in most circumstances.

Abstract: An ultra-low voltage inverter includes a first inverter, a second inverter, and third inverter. The first inverter receives an input from a delay cell and generates an output for a subsequent delay cell. The second inverter is coupled to the first inverter. The third inverter is coupled to the first inverter, wherein outputs of the second and third inverters are coupled to source terminals of a p-type transistor and an n-type transistor of the first inverter, respectively. The ultra-low voltage inverter forms a delay cell, which is a building block of an ultra-low voltage ring-oscillator. A NAND gate is formed using three inverters such that outputs of two inverters are coupled to the p-type transistors of the NAND gate, while an output of the third inverter of the three inverters is coupled to an n-type transistor of the NAND gate.

Abstract: An ultra-low voltage inverter includes a first inverter, a second inverter, and third inverter. The first inverter receives an input from a delay cell and generates an output for a subsequent delay cell. The second inverter is coupled to the first inverter. The third inverter is coupled to the first inverter, wherein outputs of the second and third inverters are coupled to source terminals of a p-type transistor and an n-type transistor of the first inverter, respectively. The ultra-low voltage inverter forms a delay cell, which is a building block of an ultra-low voltage ring-oscillator. A NAND gate is formed using three inverters such that outputs of two inverters are coupled to the p-type transistors of the NAND gate, while an output of the third inverter of the three inverters is coupled to an n-type transistor of the NAND gate.

Abstract: The integrated circuit (IC) described herein lowers the start-up voltage to, for example, 50 mV, compatible for starting a DC-DC converter from a thermoelectric generator (TEG), even with a small temperature gradient. The IC further improves end-to-end efficiency of the energy harvester by improving power efficiency of the DC-DC converter while ensuring maximum power transfer from the TEG at low voltages. The IC uses a low voltage integrated charge pump that can boost sub-100 mV input voltage. A startup clock is generated by a ring-oscillator that begins operation with low supply (e.g., 50 mV or less), and which allows for one inductor to be used for DC-DC converter and for startup of the converter. The IC can be configured between the TEG and any downstream sensor or communication circuits to provide an acceptable (e.g., greater than 1 V) voltage for powering the downstream circuits from a low-voltage (e.g., less than 200 mV) TEG energy source.

Abstract: A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

Abstract: A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.