Patents by Inventor Sourav Dutta

Sourav Dutta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240172119
    Abstract: The present invention discloses a system for controlling periodical switching of XR devices or components thereof of an UE in 5G NR communication comprising a control unit for said 5G NR communication involving a gNB and said UE, wherein the control unit further includes a resource control module (RRC) for the UE which communicates with RRC of the gNB facilitating the UE to change its media access control and a XR-specific C-DRX module for XR-specific enhancement including enabling the XR devices or components thereof to select best possible sleep mode from different sleep modes as a function of sleep duration for maximizing UE power savings.
    Type: Application
    Filed: October 11, 2023
    Publication date: May 23, 2024
    Inventors: Sourav Dutta, Dibbendu Roy, Goutam Das
  • Publication number: 20240114694
    Abstract: Backside integrated circuit capacitor structures. In an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. The first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. The transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. The second electrode can be connected to a backside interconnect feature. In some cases, the capacitor has a height that extends through at least one backside interconnect layer. In some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. The capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Sourav Dutta, Nazila Haratipour, Uygar E. Avci, Vachan Kumar, Christopher M. Neumann, Shriram Shivaraman, Sou-Chi Chang, Brian S. Doyle
  • Publication number: 20240113101
    Abstract: Techniques are provided herein to form a semiconductor device that has a capacitor structure integrated with the source or drain region of the semiconductor device. A given semiconductor device includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions. A gate structure extends in a second direction over the one or more semiconductor regions. A capacitor structure is integrated with one of the source or drain regions of the integrated circuit such that a first electrode of the capacitor contacts the source or drain region and a second electrode of the capacitor contacts a conductive contact formed over the capacitor structure. The capacitor structure may include a ferroelectric capacitor having a ferroelectric layer between the electrodes.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Sourav Dutta, Nazila Haratipour, Vachan Kumar, Uygar E. Avci, Shriram Shivaraman, Sou-Chi Chang
  • Publication number: 20240114697
    Abstract: Embodiments disclosed herein include a memory device. In an embodiment, the memory device comprises a first transistor, where the first transistor is an access transistor to write data. In an embodiment, the memory device further comprises a ferroelectric capacitor for storing data. In an embodiment, the memory device further comprises a second transistor, where the second transistor is a sense transistor to read the data stored on the ferroelectric capacitor.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Shriram SHIVARAMAN, Sou-Chi CHANG, Sourav DUTTA, Uygar E. AVCI
  • Patent number: 11914801
    Abstract: A user interface device is adapted to provide tremor cancellation. The user interface device comprises a user interface for determining a position from a physical user input and a position output for providing a time-ordered output stream of position data, but also provides a tremor learning module and a tremor cancellation module. The tremor learning module can be trained to identify tremor patterns for a user by comparing time-ordered output streams of position data produced by the user with predetermined representations. The tremor cancellation module is adapted to apply the tremor patterns learned for the user to cancel tremors in a time-ordered stream of position data produced by the user to create an output stream of position data which is corrected for user tremor. A method of training and then using such a user interface device is also described.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: February 27, 2024
    Inventors: Srinivasan Arjun Tekalur, Sourav Dutta
  • Publication number: 20240012367
    Abstract: A controller and method for controlling objects states in a complex system. A change in state of at least one first object in the system is detected. A first modifying action to the at least one first object in response to the detected change in state is determined, and output to be applied to the at least one first object. A change in state of at least one second object from the plurality of system objects different from the at least one first object is detected, where the change in state of the at least one second object is a result of the first modifying action being applied to the at least one first object. A second modifying action is determined and output to be applied to the system to improve system performance according to the performance metric after the first modifying action is applied.
    Type: Application
    Filed: November 25, 2020
    Publication date: January 11, 2024
    Inventors: Sourav DUTTA, Neil BROCKETT, Catriona CLARKE, Michele BERLINGERIO
  • Publication number: 20230281643
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating models. In some implementations, a system obtains data that comprises promotions and parameters for an opportunity. The system generates transformation spaces based on the promotions and the parameters, wherein each transformation space comprises states, each state is based on the parameters for a particular promotion. The system iterates over a number of iterations. For each transformation space, the system adjusts a state of the transformation space based on actions. The system generates a model by combining each adjusted state. The system generates an entropy for the model. The system compares the entropy to a threshold value, wherein the threshold value corresponds to one of the parameters. In response to determining that the entropy exceeds the threshold value, the system iterates. The system provides the generated model for output.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Inventors: Sourav Dutta, Sunil Kumar Singh, Sriram Subramani, Sunil Sreedharan, Anil Kharde
  • Publication number: 20230222400
    Abstract: A method of resource management for transferring resources from providers to consumers is described. The method comprises the following steps. Supply parameters for the providers and demand parameters for the consumers are established, and constraints on the allocation of the resources are also established, as is an optimisation function for determining matches between providers and consumers. The optimisation function is solved for the established constraints using a constraint-based problem solver to determine matches between providers and consumers. Resources are then transferred from providers to consumers according to the determined matches. A computing system adapted to perform this method is also described, along with a power distribution system including such a computing system.
    Type: Application
    Filed: December 17, 2020
    Publication date: July 13, 2023
    Inventors: Sourav DUTTA, Andrei MARINESCU, Leonard FEEHAN, Manoj GOKHALE, Eugene RYAN
  • Publication number: 20230112139
    Abstract: A user interface device is adapted to provide tremor cancellation. The user interface device comprises a user interface for determining a position from a physical user input and a position output for providing a time-ordered output stream of position data, but also provides a tremor learning module and a tremor cancellation module. The tremor learning module can be trained to identify tremor patterns for a user by comparing time-ordered output streams of position data produced by the user with predetermined representations. The tremor cancellation module is adapted to apply the tremor patterns learned for the user to cancel tremors in a time-ordered stream of position data produced by the user to create an output stream of position data which is corrected for user tremor. A method of training and then using such a user interface device is also described.
    Type: Application
    Filed: March 26, 2020
    Publication date: April 13, 2023
    Inventors: Srinivasan Arjun TEKALUR, Sourav DUTTA
  • Patent number: 10732350
    Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over ? with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 4, 2020
    Assignees: IMEC vzw, Katholiek Universiteit Leuven
    Inventors: Odysseas Zografos, Francky Catthoor, Sourav Dutta, Azad Naeemi
  • Patent number: 10565243
    Abstract: A transformation platform allows a common data model to provide query output to multiple types of output devices, and incorporate query responses received using multiple types of constrained user input devices, such as neural headsets, that may be used by disabled individuals. Data and software applications can employ input and output modes of a client computer device without the data or application having to be specifically formatted or programmed for the different input and output modes. The data can specify queries that include response fields having response options that are selectively, such as progressively, highlighted. A user can provide input to select a highlighted response option. For a query having multiple response fields, response options for each response field can be progressively displayed after user input is received for a current set of response options. The query responses can be stored in the data model in association with field identifiers.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 18, 2020
    Assignee: SAP SE
    Inventors: Avinash Gopala Reddy, Thomas Boulton, Ullas An, Rupali Ray, Sourav Dutta
  • Publication number: 20190064438
    Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over ? with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 28, 2019
    Inventors: Odysseas Zografos, Francky Catthoor, Sourav Dutta, Azad Naeemi
  • Patent number: 10177769
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: January 8, 2019
    Assignee: Georgia Tech Research Corporation
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Patent number: 10164641
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 25, 2018
    Assignee: Georgia Tech Research Corporation
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Publication number: 20180248554
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 30, 2018
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Publication number: 20180248553
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 30, 2018
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Publication number: 20180239501
    Abstract: A transformation platform allows a common data model to provide query output to multiple types of output devices, and incorporate query responses received using multiple types of constrained user input devices, such as neural headsets, that may be used by disabled individuals. Data and software applications can employ input and output modes of a client computer device without the data or application having to be specifically formatted or programmed for the different input and output modes. The data can specify queries that include response fields having response options that are selectively, such as progressively, highlighted. A user can provide input to select a highlighted response option. For a query having multiple response fields, response options for each response field can be progressively displayed after user input is received for a current set of response options. The query responses can be stored in the data model in association with field identifiers.
    Type: Application
    Filed: March 31, 2017
    Publication date: August 23, 2018
    Applicant: SAP SE
    Inventors: Avinash Gopala Reddy, Thomas Boulton, Ullas AN, Rupali Ray, Sourav Dutta
  • Patent number: 9979401
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: May 22, 2018
    Assignee: Georgia Tech Research Corporation
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Publication number: 20180026645
    Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 25, 2018
    Inventors: Chenyun Pan, Sourav Dutta, Azad Naeemi
  • Patent number: 8806015
    Abstract: Systems determine workload resource usage patterns of a computerized workload, using a computerized device. Such systems use the computerized device to place the computerized workload with a computer server cluster within a private cloud computing environment. Also, systems herein place the computerized workload on a selected computer server within the computer server cluster that has a resource usage pattern complementary to the workload resource usage profile, also using the computerized device. The complementary resource usage pattern peaks at different times from the workload resource usage patterns.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sourav Dutta, Akshat Verma, Balaji Viswanathan