Abstract: Exemplary embodiments of the present invention pertain to circuitry provided in a digital-to-analog converter (DAC) for carrying out measurements indicative of various performance characteristics of the DAC. In one exemplary implementation, a control circuit containing one or more switches is used to controllably route into a measurement system, a portion of a signal that straddles a boundary between a first digital data bit and a second digital data bit in a sequence of digital data bits that are received in a DAC cell of the DAC. The control circuit, which can be included in one or more DAC cells of the DAC, is connected to a branch of a differential circuit that is provided in each of the DAC cells of the DAC, in a manner that does not affect digital-to-analog conversion in the DAC cells.

Abstract: A system and method for detecting and correcting large errors during ADC operation. The system includes an ADC; an AAF at the input of the ADC, having bandwidth less than information bandwidth of the ADC; and a large-error detection and correction processing unit at the output of the ADC. The large-error detection and correction circuit includes an interpolation filter to determine values of predicted digital samples corresponding to actual digital samples in a sequence of digital samples from the ADC based on information from neighboring digital samples. A signal-delay circuit in parallel with the interpolation filter delays the actual digital samples by an amount of a lag from the interpolation filter. An adder determines differences between the predicted and actual digital samples, a matched filter detects a pattern of the differences, and a large-error detection processing unit determines whether a large error occurs based on the pattern of the differences.

Abstract: An analog input signal is dithered using a dithering sequence and then partially chopped using a chopping sequence. The dithered and partially chopped signal is then digitized by analog-to-digital converter (ADC) slices operating in alternating fashion, and the resulting digitized signals are adjusted according to the dithering sequence and the chopping sequence to compensate for gain and voltage offset errors of the ADC slices.

Abstract: An offset compensated comparator 70 has capacitors 80 and 81 coupled directly between the inputs of a preamplifier 78 and the outputs of a previous stage amplifier 62. The comparator 70 also includes additional capacitors 82 and 83 coupled between the inputs of the preamplifier 78 and reference voltage nodes VREFP and VREFM. Switches 73 and 74 are coupled between the additional capacitors 82 and 83 and the reference voltage nodes VREFP and VREFM. An additional switch 72 is coupled between the additional capacitors 82 and 83. In this configuration, there are no series sampling switches between the previous stage amplifier 62 and the comparator 70. Eliminating the series switches reduces the load seen by the previous stage amplifier 62, which allows the previous stage amplifier 62 to have a faster settling time. This allows the current in the previous stage amplifier 62 to be decreased which reduces the power consumption.