Abstract: Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the gate. For some disclosed embodiments, a select gate is formed before a control gate. For other disclosed embodiments, the control gate is formed before the select gate. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.

Abstract: Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the select gate. For some disclosed embodiments, a select gate is formed before a control gate for the split-gate NVM cell. For other disclosed embodiments, the control gate is formed before the select gate for the split-gate NVM cell. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.

Abstract: A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.

Abstract: A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.

Abstract: A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

Abstract: A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

Abstract: A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.

Abstract: A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.