Patents by Inventor Spencer Gold
Spencer Gold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160336054Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Stephen FELIX, Hwong-Kwo LIN, Spencer GOLD, Jing GUO, Andreas GOTTERBA, Jason GOLBUS, Karthik NATARAJAN, Jun YANG, Zhenye JIANG, Ge YANG, Lei WANG, Yong LI, Hua CHEN, Haiyan GONG, Beibei REN, Eric VOELKEL
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Patent number: 9484115Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.Type: GrantFiled: May 13, 2015Date of Patent: November 1, 2016Assignee: NVIDIA CorporationInventors: Stephen Felix, Hwong-Kwo Lin, Spencer Gold, Jing Guo, Andreas Gotterba, Jason Golbus, Karthik Natarajan, Jun Yang, Zhenye Jiang, Ge Yang, Lei Wang, Yong Li, Hua Chen, Haiyan Gong, Beibei Ren, Eric Voelkel
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Patent number: 9390788Abstract: An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.Type: GrantFiled: July 27, 2015Date of Patent: July 12, 2016Assignee: Nvidia CorporationInventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
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Publication number: 20150332757Abstract: An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Inventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
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Patent number: 9123438Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.Type: GrantFiled: October 15, 2013Date of Patent: September 1, 2015Assignee: Nvidia CorporationInventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
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Publication number: 20150103584Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.Type: ApplicationFiled: October 15, 2013Publication date: April 16, 2015Applicant: Nvidia CorporationInventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
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Patent number: 8456945Abstract: A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively.Type: GrantFiled: April 23, 2010Date of Patent: June 4, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Spencer Gold, Stephen V. Kosonocky, Samuel Naffziger
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Patent number: 8176352Abstract: Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.Type: GrantFiled: April 16, 2008Date of Patent: May 8, 2012Assignee: Adavanced Micro Devices, Inc.Inventors: Kevin Gillespie, Guhan Krishnan, Maurice Steinman, Spencer Gold, Bill K. C. Kwan
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Publication number: 20110261064Abstract: A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively.Type: ApplicationFiled: April 23, 2010Publication date: October 27, 2011Inventors: Spencer Gold, Stephen V. Kosonocky, Samuel Naffziger
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Publication number: 20090261869Abstract: Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Kevin GILLESPIE, Guhan KRISHNAN, Maurice STEINMAN, Spencer GOLD, Bill K.C. KWAN
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Patent number: 6937958Abstract: A controller and method are provided for monitoring and controlling a temperature of an integrated circuit to inhibit damage from a thermal problem. The controller and method allow for individual temperature thresholds for each of one or more temperature sensors. Digital filtering of values received from temperature sensors is also provided. A variety of actions can be selected for execution upon a determination of an over-temperature condition of the integrated circuit, including assert an over-temperature pin, assert an over-temperature bit in an error register of said controller, assert an over-temperature bit in an error register of said microprocessor, issue an over-temperature interrupt to a service bus of said integrated circuit, cause a trap, slow an operating frequency of said integrated circuit, stop said integrated circuit, and do nothing.Type: GrantFiled: February 19, 2002Date of Patent: August 30, 2005Assignee: Sun Microsystems, Inc.Inventors: Spencer Gold, Claude R. Gauthier, Kenneth House, Kamran Zarrineh
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Patent number: 6809557Abstract: An apparatus that uses a linear voltage regulator to reject power supply noise in a temperature sensor is provided. Further, a method for using a linear voltage regulator to reject power supply noise in a temperature sensor is provided. Further, a method and apparatus that uses a differential amplifier with a source-follower output stage as a linear voltage regulator for a temperature sensor is provided.Type: GrantFiled: February 19, 2002Date of Patent: October 26, 2004Assignee: Sun Microsystems, Inc.Inventors: Claude Gauthier, Spencer Gold, Dean Liu, Kamran Zarrineh, Brian Amick, Pradeep Trivedi
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Patent number: 6806698Abstract: A method and apparatus that uses the difference between two nodal voltages, such as a temperature-independent voltage and a temperature-dependent voltage, to determine the actual temperature at a point on an integrated circuit is provided. Further, a method and apparatus that converts a difference between nodal voltages in an integrated circuit from an analog to a digital quantity on the integrated circuit such that the difference in voltage may be used by an on-chip digital system is provided. Further, a method and apparatus for quantifying a difference in voltage between a first node and a second node of a temperature sensor is provided.Type: GrantFiled: February 19, 2002Date of Patent: October 19, 2004Assignee: Sun Microsystems, Inc.Inventors: Claude Gauthier, Brian Amick, Spencer Gold, Dean Liu, Kamran Zarrineh, Pradeep Trivedi
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Patent number: 6775638Abstract: A temperature sensor adapted to produce a temperature-independent voltage and temperature-dependent voltage dependent on an internal control signal, generated within the temperature sensor, adjustable by an adjustment circuit operatively connected to the temperature sensor is provided. The adjustment circuit is controllable to adjust the internal control signal in order to modify an operating characteristic of the temperature sensor.Type: GrantFiled: April 24, 2002Date of Patent: August 10, 2004Assignee: Sun Microsystems, Inc.Inventors: Claude Gauthier, Brian Amick, Spencer Gold, Pradeep Trivedi, Lynn Ooi
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Patent number: 6749335Abstract: An adjustment and calibration system for post-fabrication treatment of an on-chip temperature sensor is provided. As explained in detail below, the adjustment and calibration system includes at least one adjustment circuit, to which the on-chip temperature sensor is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.Type: GrantFiled: May 17, 2002Date of Patent: June 15, 2004Assignee: Sun Microsystems, Inc.Inventors: Claude Gauthier, Brian Amick, Spencer Gold, Pradeep Trivedi, Lynn Ooi
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Publication number: 20030214998Abstract: An adjustment and calibration system for post-fabrication treatment of an on-chip temperature sensor is provided. As explained in detail below, the adjustment and calibration system includes at least one adjustment circuit, to which the on-chip temperature sensor is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.Type: ApplicationFiled: May 17, 2002Publication date: November 20, 2003Inventors: Claude Gauthier, Brian Amick, Spencer Gold, Pradeep Trivedi, Lynn Ooi
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Publication number: 20030204358Abstract: A temperature sensor adapted to produce a temperature-independent voltage and temperature-dependent voltage dependent on an internal control signal, generated within the temperature sensor, adjustable by an adjustment circuit operatively connected to the temperature sensor is provided. The adjustment circuit is controllable to adjust the internal control signal in order to modify an operating characteristic of the temperature sensor.Type: ApplicationFiled: April 24, 2002Publication date: October 30, 2003Inventors: Claude Gauthier, Brian Amick, Spencer Gold, Pradeep Trivedi, Lynn Ooi
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Patent number: 6628135Abstract: An on-chip voltage sensor that selectively eliminates noise from a voltage measurement is provided. The on-chip voltage sensor has resistive and capacitive components in the voltage divider, thus allowing a voltage on a section of a computer chip to be measured exclusive of high-frequency noise. Further, a method for measuring a voltage on a section of a computer chip using a voltage divider having a resistor and a capacitor is provided. Further, a computer chip having an on-chip voltage sensor is provided. Further, a method and apparatus for observing voltages at multiple locations on an integrated circuit.Type: GrantFiled: September 18, 2001Date of Patent: September 30, 2003Assignee: Sun Microsystems, Inc.Inventors: Claude R. Gauthier, Brian W. Amick, Spencer Gold
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Publication number: 20030167428Abstract: A method is provided to perform spatial locality testing on a memory array having a logical address map distinct from its physical address map. The built-in self-test generator performs memory spatial locality tests on the memory array by generating adjacent physical memory row addresses that are then converted to corresponding logical memory row addresses. Once the physical memory row address is converted to its corresponding memory row address the test vector is written to the logical memory row address to perform spatial locality tests on adjacent physical memory row addresses of the memory array.Type: ApplicationFiled: April 13, 2001Publication date: September 4, 2003Applicant: SUN MICROSYSTEMS, INCInventor: Spencer Gold
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Publication number: 20030155964Abstract: An apparatus that uses a linear voltage regulator to reject power supply noise in a temperature sensor is provided. Further, a method for using a linear voltage regulator to reject power supply noise in a temperature sensor is provided. Further, a method and apparatus that uses a differential amplifier with a source-follower output stage as a linear voltage regulator for a temperature sensor is provided.Type: ApplicationFiled: February 19, 2002Publication date: August 21, 2003Inventors: Claude Gauthier, Spencer Gold, Dean Liu, Kamran Zarrineh, Brian Amick, Pradeep Trivedi