Abstract: A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.

Abstract: A hierarchical traffic policer may include a first policer configured to pass first packets when a first condition is met. The first policer also may alter selection information within the passed first packets. A second policer may be configured to pass second packets when a second condition is met. The second policer may be further configured to pass all of the passed first packets from the first policer based on the altered selection information within the passed first packets.

Abstract: A data processing system performs any-to-any transmission of data blocks. The system receives the data blocks on incoming data streams, and load balances the data blocks across a number of processing paths. The processing paths process the data blocks causing one or more of the data blocks to become out of order relative to an order in which the data blocks were received. The system hashes the data blocks to determine a manner in which to transmit the data blocks, reorders the data blocks to restore the order in which the data blocks were received, and transmits the reordered data blocks on outgoing data streams.

Abstract: A system precomputes data for possible use by a processor. The system receives data units, and determines the types of the data units. The system then identifies one or more bit masks based on the types of the data units, where the one or more bit masks include bits corresponding to at least some portions of the data units. The system uses the one or more bit masks to select one or more portions of the data units and perform one or more functions using the one or more portions of the data units to generate function results. The system stores the function results in a first memory for subsequent selective use by the processor, and stores the data units in a second memory for subsequent retrieval by the processor.

Abstract: A network device provides services for multiple virtual private networks (VPNs) via one or more virtual hosts. For example, a router receives packets from multiple VPNs, and communicates the packets to a service card via a logical interface in accordance with a forwarding information base. A virtual host within the service card processes the packets and provides a service for the network device from which the packet was sent. The virtual host may, for example, provide print services for network devices within a corresponding VPN. The virtual host acts, in essence, as a print server within the corresponding VPN. In this manner, the router may eliminate the need for the customer associated with the VPN to maintain print servers within remote customer sites.

Abstract: Transparent wavelength division multiplexing systems and methods include an array of wavelength converters receiving n input signals and shifting the wavelength of each input signal by a different amount so that n different wavelengths result. Each of the wavelength converters shifts the wavelength of the input signal by a known amount. The resulting signals may be combined and transmitted over a fiber. A passive (or active) wavelength splitter may be used to recover the signals from the fiber, and deliver the signals directly to one or more network devices. Receivers in the receiving router or switch generally are not wavelength-specific, so the n optical signals need not be shifted back to a common wavelength prior to the router or switch.

Abstract: According to one embodiment, an encryption system (500) includes an input buffer (504) that can provide data blocks from different contexts (522-1 to 522-n) to a selected encryption circuit (524-1 to 524-m) according to a scheduling section (502). A scheduling section (502) can include a register array (510) having rows that each correspond to a context and columns that correspond to an encryption circuit. Each register array (510) row can store one “hot” bit that designates a context with a particular encryption circuit. A column can be selected by a multiplexer (514) and its values prioritized and encoded by a priority encoder (518) to generate an address that results in the selection of a data block from a particular context. Priority may be varied by shifting a column value with a rotate circuit (516) according to an offset value (OFFSET).

Abstract: A system for providing multiple field matching capabilities for network data packets is disclosed. According to one embodiment (700) the system includes a number of prefix engines (704-0, 704-1, 712-0 and 712-1) coupled together in a pipelined fashion. First level prefix engines (704-0 and 704-1) perform longest prefix matching operations on address values (Dest-IP and Src-IP) and provide address equivalence class values (daclass and saclass). The address class equivalence values (daclass and saclass) are combined with port identification values (Dest-Port and Src-Port) and applied to second level prefix engines (712-0 and 712-1) which provide tuple equivalence class values (dtclass and stclass). The tuple equivalence class values (dtclass and stclass) are combined and applied to an output mapping circuit (718) which provides a flow specification value corresponding to each applied set of address (Dest-IP and Src-IP) and port (Dest-Port and Src-Port) values.

Abstract: According to one embodiment (100) a system may receive a multi-bit input value (DEST_IP) and split it into a number of portions (L1bits, L2bits and L3bits). A first portion (L1bits) can generate a first address (A1) that accesses a first array (116). A first array (116) can provide output values or second array pointer values. Second array pointer values may be combined with a second portion (L2bits) to generate a second address (A2). A second address (A2) can access a second array (118). A second array (118) can provide output values or third array pointer values. Third array pointer values may be combined with a third portion (L3bits) to generate a third address (A3). A third address (A3) can access a third array (120) which can provide output values.

Abstract: A system and method form searching an associative memory using input key values and first and second hashing sections. Key values (Kn) can be hashed in the first hashing section (102) to generate first output values H1(Kn) that access a first store (104). The first store or memory portion (104) can include “leaf” pointer entries (106-2) and “chunk pointer” entries (106-3). A leaf pointer entry (106-2) points at data associated with an applied key value. A chunk pointer entry (106-3) includes pointer data. If a chunk pointer entry (106-3) is accessed, the key value (Kn) is hashed in the second hashing section (108) to generate second output values H2(Kn) that access a second store or memory portion (110). Second hashing section (108) hashes key values (Kn) according to selection data SEL stored in a chunk pointer entry (106-3).

Abstract: A method and apparatus for dynamically regrouping display memory chips to efficiently implement 8-bit, 16-bit, and 24-bit per pixel display solutions is provided. The invention permits the implementation of 24-bit per pixel solutions in which 24-bit pixels do not straddle addressable regions, but without requiring the use of a unused byte of display memory per 24-bit pixel.