Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.

Abstract: Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.

Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.

Abstract: A system and method for using unreachable states of a circuit design in a testing mode to increase random testability of a random resistant logic circuit. Control-improving logic circuitry is integrated into a logic circuit design to improve its testability and will not affect behavior of the design in its functional mode (by remaining “inactive” in the functional mode of the integrated circuit). The control-improving logic circuitry is automatically activated in testing mode. The control improving logic circuit is generated selectively for random resistant logic circuit regions that exhibit limited controllability in the functional mode and improves controllability of random resistant logic in the testing mode. The improved controllability results from activating test circuitry in the states that are not reachable during normal functionality.

Abstract: Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.

Abstract: A system and method for using unreachable states of a circuit design in a testing mode to increase random testability of a random resistant logic circuit. Control-improving logic circuitry is integrated into a logic circuit design to improve its testability and will not affect behavior of the design in its functional mode (by remaining “inactive” in the functional mode of the integrated circuit). The control-improving logic circuitry is automatically activated in testing mode. The control improving logic circuit is generated selectively for random resistant logic circuit regions that exhibit limited controllability in the functional mode and improves controllability of random resistant logic in the testing mode. The improved controllability results from activating test circuitry in the states that are not reachable during normal functionality.

Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.

Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.