Abstract: Data stored in SRAM cells are periodically flipped e.g., before long idle periods. Operating the memories in both a ‘flipped’ mode and a ‘non-flipped’ mode helps cause the Bias Temperature Instability (BTI) degradation to be symmetric, thereby not degrading the Static Noise Margin (SNM) degradation of the cells. The data stored in memory locations is flipped by reading out the data, inverting the read out data, and writing the inverted read out data into the memory locations until the memory locations of the SRAM have been read out and written. When the memory operates in flipped mode, data read from and written into the memory is inverted to maintain transparency to the memory user. After operating the data in flipped mode for a period of time, the flipped data stored in the memory is reflipped to operate in the non-flipped mode.

Abstract: A method is provided in which a first error test may be performed on a memory that includes an integrated error correcting code (ECC) portion. The functionality of the ECC portion may be bypassed in the first error test. A second error test may be performed on the memory, where the second error test includes testing the functionality of the ECC portion. Also provided is an apparatus including a memory device and an error correcting code (ECC) circuit. The apparatus also includes a first switching device adapted to select a first input signal or a second input signal and a second switching device adapted to select one of a signal from the memory device or a signal from a portion of the ECC circuit. Also provided are computer readable storage devices encoded with data for adapting a manufacturing facility to create the apparatus and for adapting a processor to perform the method above.

Abstract: Data stored in SRAM cells are periodically flipped e.g., before long idle periods. Operating the memories in both a ‘flipped’ mode and a ‘non-flipped’ mode helps cause the Bias Temperature Instability (BTI) degradation to be symmetric, thereby not degrading the Static Noise Margin (SNM) degradation of the cells. The data stored in memory locations is flipped by reading out the data, inverting the read out data, and writing the inverted read out data into the memory locations until the memory locations of the SRAM have been read out and written. When the memory operates in flipped mode, data read from and written into the memory is inverted to maintain transparency to the memory user. After operating the data in flipped mode for a period of time, the flipped data stored in the memory is reflipped to operate in the non-flipped mode.

Abstract: A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.

Abstract: A method is provided in which a first error test may be performed on a memory that includes an integrated error correcting code (ECC) portion. The functionality of the ECC portion may be bypassed in the first error test. A second error test may be performed on the memory, where the second error test includes testing the functionality of the ECC portion. Also provided is an apparatus including a memory device and an error correcting code (ECC) circuit. The apparatus also includes a first switching device adapted to select a first input signal or a second input signal and a second switching device adapted to select one of a signal from the memory device or a signal from a portion of the ECC circuit. Also provided are computer readable storage devices encoded with data for adapting a manufacturing facility to create the apparatus and for adapting a processor to perform the method above.

Abstract: A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.

Abstract: A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.

Abstract: A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.

Abstract: Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency.

Abstract: A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.

Abstract: The present invention provides methods and memory structures for efficient tracking and recycling of physical register assignments. The disclosed methods and memory structures each provide an approach to reduce the size of the memory structures needed to track the usage of the physical registers and the recycling of these registers.

Abstract: A method and apparatus is provided for restoring a free physical register list to its previous state without having to physically restore any data. The method and semiconductor device utilizes sets of pointers to manage physical register pointers in the physical register list. The physical register list is able to independently track physical registers for multiple threads of a multithreading microprocessor.

Abstract: A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

Abstract: A system and method for memory structures for efficient tracking and recycling of physical register assignments are disclosed. The method and system provide the necessary functionality to allow the number of physical registers assigned to incoming instructions to equal the number of physical registers that are returned to the list of free registers each cycle, thereby maintaining a substantially constant number of physical register pointers in the list of free registers. The system and method reduce the size of the memory structures utilized to track the usage of physical registers and the recycling of these registers.

Abstract: An apparatus and method are provided for sensing a physical stimulus of an integrated circuit. The apparatus and method allow for accurate die temperature measurements of the integrated circuit and are able to provide a highly accurate die temperature measurement without the need for an independent voltage source or current source.

Abstract: A sensor and method are provided for sensing a physical stimulus in an integrated amount, such as thermal energy and produce a signal that indicates a quantitative value of the physical stimulus along with a value that indicates the operability of the sensor and a value that indicates a sense operation is in process. The sensor and method minimize the number of input and output pins necessary for a sensor to report a measurement response of a physical stimulus.

Abstract: A memory array or structure and method for decoding a read address to facilitate simultaneous reading of successive rows. The memory includes row decoders in the form of decoding logic for enabling multiple rows of the memory structure to be read in response to a single row address. The memory structure helps to reduce the number of ports that are required for the memory structure and, thus, reduces the die area occupied by the memory structure. The row address may be divided into most significant bits and least significant bits. Further, the decoding logic may decode the most significant bits differently from the least significant bits when processing the row address. The most significant bits may be preprocessed or predecoded into a fully decoded format while the least significant bits may be decoded into a priority decoded format.

Abstract: A method and apparatus are provided for depositing a filler material in a physical layout for an integrated circuit. The filler material is deposited on a layer by layer basis in the physical layout so that a channel length of the filler material has an orientation that differs between immediately adjacent layers. In addition, the filler materials in each of the layers are grouped into a first group and a second group wherein the filler material associated with the first group is coupled to a first portion of a power grid in the integrated circuit and the filler material associated with the second group is coupled to a second portion of the power grid in the integrated circuit. The tiller materials associated with each group are interconnected using one or more vias so that the filler material is capable of expanding the power grid of the integrated circuit to assist in the distribution of power throughout the various layers of the integrated circuit.

Abstract: The present invention provides a system and method for memory structures for efficient tracking and recycling of physical register assignments. The system and method reduce the size of the memory structures utilized to track the usage of physical registers and the recycling of these registers.

Abstract: A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.