Abstract: The methods and systems are directed to automated computer analysis and machine learning. Specifically, the systems and methods for using machine learning to generate fault prediction models and applying the fault prediction models to logical circuits to optimize test point insertion determinations and optimize fault detection in the logical circuit. Disclosed are methods and systems that that generates training data from training circuits (and optionally generate training circuits), trains a learning segment (which may include an artificial neural network (ANN)) using the training data. The learning segment (once trained) generates fault prediction models to predict the quality of a TP inserted on a given circuit location and optimize TPI for a given circuit. The methods and systems described provide computational (CPU/processing) time advantages and precision over conventional methods.

Abstract: A system for creating protected functional descriptions of integrated circuits provides an encrypted functional description that allows the integrated circuit to be simulated with respect to producing outputs for given sets of inputs without identification of the constituent components of the integrated circuit such as the logical gates making up the integrated circuit. The encrypted functional description may include encrypted truth-tables describing the generic gates of the integrated circuit, the encrypted truth-tables securing the function of each logical gate by including multiple redundant table entries mapped to alias values of Boolean logical states and erroneous table entries.

Abstract: A system for creating protected functional descriptions of integrated circuits provides an encrypted functional description that allows the integrated circuit to be simulated with respect to producing outputs for given sets of inputs without identification of the constituent components of the integrated circuit such as the logical gates making up the integrated circuit. The encrypted functional description may include encrypted truth-tables describing the generic gates of the integrated circuit, the encrypted truth-tables securing the function of each logical gate by including multiple redundant table entries mapped to alias values of Boolean logical states and erroneous table entries.