Abstract: Automatic test equipment (ATE) configured to test devices under test (DUTs) can include a host device tester, one or more load boards, and one or more host bus adapters (HBAs). The host device tester does not support odd sector sizes and/or non-standard sector sizes. The one or more load boards can be communicatively coupled to the host device. The one or more HBAs can be communicatively coupled between respective load boards and one or more respective devices under test (DUTs). The one or more load boards can be configured to communicate with respective HBAs using one or more first communication protocol interfaces. The one or more HBAs can be configured to communicate with the respective DUTs using one or more second communication protocol interfaces. The HBAs can be configured to translate commands and data between the host device tester and the one or more DUTs that support odd sector size or non-standard sector size.

Abstract: Device testing techniques including allocating a log memory, testing a device, and storing test result during testing of the device in the allocated log memory. The allocated log memory can be accessed through an application programming interface (API) during testing of the device, wherein the allocated log memory remains unlocked during testing of the device.

Abstract: Embodiments of the present invention can provide an extended NVMe driver that supports exercising virtual functions (and related physical functions) of a DUT without using a VM or hypervisor. In this way, the amount of memory and processing resources used for testing NVMe SSDs can be significantly reduced, and a large number of DUTs (e.g., up to 16 DUTs) can be tested in parallel independently. In other words, each DUT is tested in isolation, as if is the only device being tested, and there are no race conditions or competition for resources between workloads during testing.

Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation.

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester includes a direct access device (DAX) interface that prevents corruption of DUTs. In one exemplary implementation, the tester isolates testing of a particular CXL enabled DUT from undesirable interference and corruption. The tester can prevent inappropriate writing over the DUT's memory. The DUTs reside in the separate per-device space of a Linux operating system rather than an extension of memory space. One of the plurality of DUTs can be a CXL type 3 memory expander device.

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing flexible and independent parallel testing across the plurality of DUTs. In one exemplary implementation, the tester generates and manages workloads independently for DUTs included in the plurality of DUTs. The DUTs can be memory devices the tester is configured to test different memory spaces in parallel. The different memory spaces can have various implementations (e.g., included in the plurality of DUTs, different memory spaces are within one of the DUTs included in the plurality of DUTs, etc.).

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester is configured to enable hot add of one of the plurality of DUTs without interfering with testing of the other DUTS. In one exemplary implementation, the DUTs are memory devices and the DUTs can operate as extended memory. The user interface can be utilized to indicate a pause to remove a DUT and to indicate a DUT has been added and to trigger a re-start. The added one of the plurality of DUTs can be automatically recognized by a host in a way that is transparent to users. The tester automatically directs the hot add in response to a user trigger.

Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs), and a hardware interface board coupled to the test computer system and controlled by the test computer system. The hardware interface board is operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs, the hardware interface board including: a processor operable to access test pattern data for application to a DUT.

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a testing system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing. In one exemplary implementation, the tester prevents testing of a first one of the plurality of DUTs from detrimentally interfering with testing of a second one of the plurality of DUTs.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, an enhanced auxiliary interface test system comprises a load board, testing electronics, controller, and memory mapped interface. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics is configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics. The memory mapped interface is configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: Embodiments of the present invention provide systems and methods for automatically performing DUT testing on a large number of ZNS SSDs in parallel and in accordance with the configuration and restrictions associated with the various zones that comprise the address space of the ZNS SSDs. A computer process detects ZNS devices and their characteristics (e.g., zone parameters) and uses novel methods of executing read and write tests that can test unique features of ZNS devices. For example, some embodiments perform efficient and effective testing controls that account for numerous differences in ZNS characteristics and geometries between different device models. Embodiments can track the states of a large number of zones and handle each zone based on predetermined test specifications.

Abstract: An automated test equipment (ATE) system comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor, wherein the system controller is operable to transmit instructions to the tester processor. The tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT), wherein the DUT supports an arbitrary sector size, and wherein software layers on the tester processor perform computations to be able control data flow between the tester processor and sectors of arbitrary size in the DUT.

Abstract: Non-standard sector size system support for SSD testing. An automated test equipment for simultaneous testing of multiple solid state drives (SSDs), wherein the SSD has a sector size that is not an integral power of two, includes a tester block configured to receive a command to read and verify an amount of data from the SSD starting at a starting address. The starting address is not constrained to correspond to a sector boundary and the amount of data is not constrained to be an integral multiple of the SSD data sector size. The test equipment also includes logic within said tester block configured to determine a starting sector of the SSD that the starting address points to, and logic within said tester block configured to determine a number of sectors required for the amount of data to be read. The tester block is configured to read a sector from the SSD.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, an enhanced auxiliary interface test system comprises a load board, testing electronics, controller, and memory mapped interface. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics is configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics. The memory mapped interface is configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.