Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

Abstract: During a testing of a circuit design, an adaptive clock model and a voltage noise model are utilized within the computer implemented method of the testing environment in order to determine the dynamic effects of voltage variation and adaptive clock on the timing of the circuit design. The computer implemented method uses a hybrid stage that incorporates both a graph-based approach and a path-based approach may also be incorporated into the testing environment in order to maximize a performance of the testing of the circuit design.

Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

Abstract: A computer-implemented method for designing an integrated circuit includes determining a timing slack associated with a first cell of the integrated circuit that is physically adjacent to a second cell of the integrated circuit, the second cell including an implant region that is in violation of an implant width design rule associated with the integrated circuit, determining that the timing slack is greater than a change in timing slack associated with expanding the implant region into the first cell, and, in response, expanding the implant region from first cell into the second cell to form a larger implant region.

Abstract: A computer-implemented method for designing an integrated circuit includes determining a timing slack associated with a first cell of the integrated circuit that is physically adjacent to a second cell of the integrated circuit, the second cell including an implant region that is in violation of an implant width design rule associated with the integrated circuit, determining that the timing slack is greater than a change in timing slack associated with expanding the implant region into the first cell, and, in response, expanding the implant region from first cell into the second cell to form a larger implant region.