Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.

Abstract: Periodic signal timing calibration is implemented in time-distributed fragments executed concurrently with occasional system-idling maintenance operations to maintain reliable synchronous communication between interconnected system components without impacting system availability.

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.

Abstract: Periodic signal timing calibration is implemented in time-distributed fragments executed concurrently with occasional system-idling maintenance operations to maintain reliable synchronous communication between interconnected system components without impacting system availability.

Abstract: System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information.

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.