Abstract: Apparatus and methods for setting wakeup times in a communication device are disclosed where setting the wakeup times includes estimating the lock on time of a frequency synthesizer in order to minimize the wakeup time and extend sleep times for maximal energy savings. A disclosed apparatus includes an estimator to receive a current lock on time of a frequency synthesizer, which is the time taken by the frequency synthesizer to lock on to particular frequency after a wakeup signal has been issued to turn on the synthesizer after a sleep period. The estimator calculates a latest estimated lock on time based at least on the current lock on time of the frequency synthesizer and determines an enable signal timing information based on the estimated lock on time. The apparatus also includes a timer configured to receive the enable signal timing information and issue at least one enable signal to turn on other circuitry in the transceiver after the synthesizer lock on period based thereon.

Abstract: Apparatus and methods for an interface are disclosed. In particular, an apparatus for handling hardware requests over an interface between a hardware circuit and another circuit, such as a radio frequency integrated circuit (RFIC) is disclosed. The hardware request controller apparatus utilizes a configuration memory that receives and stores data concerning memory address locations within a data memory, also within the controller. The data memory receives and stores read or write data used for reading data from and writing data to the other circuit. The controller apparatus also includes master state machine logic that receives the hardware request commands from the hardware circuit and determines which address locations are to be accessed in the data memory based on the data concerning memory locations stored in the configuration memory.

Abstract: Apparatus and methods for setting wakeup times in a communication device are disclosed where setting the wakeup times includes estimating the lock on time of a frequency synthesizer in order to minimize the wakeup time and extend sleep times for maximal energy savings. A disclosed apparatus includes an estimator to receive a current lock on time of a frequency synthesizer, which is the time taken by the frequency synthesizer to lock on to particular frequency after a wakeup signal has been issued to turn on the synthesizer after a sleep period. The estimator calculates a latest estimated lock on time based at least on the current lock on time of the frequency synthesizer and determines an enable signal timing information based on the estimated lock on time. The apparatus also includes a timer configured to receive the enable signal timing information and issue at least one enable signal to turn on other circuitry in the transceiver after the synthesizer lock on period based thereon.