Patents by Inventor Sreenivasulu Reddy Vedicherla

Sreenivasulu Reddy Vedicherla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Eigen augmentation methods for electromagnetic modelling and simulation
    Patent number: 11244094
    Abstract: Techniques for electromagnetic modelling of EM structures are described. Krylov subspace of a second EM structure is augmented with Eigen vectors of a first EM structure to form an augmented space. The second EM structure is a design variant of the first EM structure and the first EM structure is already EM modelled and simulated. Thereafter, Maxwell's equations for the second EM structure are solved using the augmented space.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 8, 2022
    Assignees: INDIAN INSTITUTE OF SCIENCE, ROBERT BOSCH ENGINEERING AND BUSINESS SOLUTIONS PRIVATE LIMITED
    Inventors: Dipanjan Gope, Gourav Chatterjee, Arkaprovo Das, Sreenivasulu Reddy Vedicherla
  • EIGEN AUGMENTATION METHODS FOR ELECTROMAGNETIC MODELLING AND SIMULATION
    Publication number: 20190236227
    Abstract: Techniques for electromagnetic modelling of EM structures are described. Krylov subspace of a second EM structure is augmented with Eigen vectors of a first EM structure to form an augmented space. The second EM structure is a design variant of the first EM structure and the first EM structure is already EM modelled and simulated. Thereafter, Maxwell's equations for the second EM structure are solved using the augmented space.
    Type: Application
    Filed: July 18, 2017
    Publication date: August 1, 2019
    Inventors: Dipanjan GOPE, Gourav CHATTERJEE, Arkaprovo DAS, Sreenivasulu Reddy VEDICHERLA
  • Methods for detecting a hidden peak in wire fault location applications—improving the distance range resolution
    Patent number: 8324906
    Abstract: Hidden or overlapped peaks may occur when using SSTDR technology to determine ware faults. These hidden/overlapped peaks may cause false negative determinations (no fault) when testing a wire for faults. In one method of the present invention, the symmetrical property of the SSTDR wave envelope is used to resolve hidden/overlapped peaks. In another method of the present invention, the calibrated normalized loop back SSTDR wave envelope may be used to resolve hidden/overlapped peaks.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: December 4, 2012
    Assignee: Honeywell International Inc.
    Inventors: Shaik Shafi Ahamed, Srinivasa Rao Dangeti, Narasimha Rao Pesala, Thappeta Peddaiah, Sreenivasulu Reddy Vedicherla, Vedagiribabu Subramanyam, Zhenning Liu
  • METHODS FOR DETECTING A HIDDEN PEAK IN WIRE FAULT LOCATION APPLICATIONS - IMPROVING THE DISTANCE RANGE RESOLUTION
    Publication number: 20110227582
    Abstract: Hidden or overlapped peaks may occur when using SSTDR technology to determine ware faults. These hidden/overlapped peaks may cause false negative determinations (no fault) when testing a wire for faults. In one method of the present invention, the symmetrical property of the SSTDR wave envelope is used to resolve hidden/overlapped peaks. In another method of the present invention, the calibrated normalized loop back SSTDR wave envelope may be used to resolve hidden/overlapped peaks.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 22, 2011
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: SHAIK SHAFI AHAMED, SRINIVASA RAO DANGETI, NARASIMHA RAO PESALA, THAPPETA PEDDAIAH, SREENIVASULU REDDY VEDICHERLA, VEDAGIRIBABU SUBRAMANYAM, ZHENNING LIU