Patents by Inventor Sreeram Appasamy

Sreeram Appasamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8420978
    Abstract: A high-throughput, low cost, patterning platform is provided that is an alternative to conventional photolithography and direct laser ablation patterning techniques. The processing methods are useful for making patterns of microsized and/or nanosized structures having accurately selected physical dimensions and spatial orientation that comprise active and passive components of a range of microelectronic devices. Processing provided by the methods is compatible with large area substrates, such as device substrates for semiconductor integrated circuits, displays, and microelectronic device arrays and systems, and is useful for fabrication applications requiring patterning of layered materials, such as patterning thin film layers in thin film electronic devices.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: April 16, 2013
    Assignees: The Board of Trustees of the University of Illinois, Anvik Corporation
    Inventors: Kanti Jain, Junghun Chae, Sreeram Appasamy
  • Publication number: 20080176398
    Abstract: Methods of the present invention provide a high-throughput, low cost, patterning platform that is an alternative to conventional photolithography and direct laser ablation patterning techniques. The present processing methods are useful for making patterns of microsized and/or nanosized structures having accurately selected physical dimensions and spatial orientation that comprise active and passive components of a range of microelectronic devices. Processing provided by the present methods is compatible with large area substrates, such as device substrates for semiconductor integrated circuits, displays, and microelectronic device arrays and systems, and is useful for fabrication applications requiring patterning of layered materials, such as patterning thin film layers in thin film electronic devices.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 24, 2008
    Inventors: Kanti Jain, Junghun Chae, Sreeram Appasamy
  • Publication number: 20050067286
    Abstract: Various techniques for the fabrication of highly accurate master molds with precisely defined microstructures for use in plastic replication using injection molding, hot embossing, or casting techniques are disclosed herein. Three different fabrication processes used for master mold fabrication are disclosed wherein one of the processes is a combination of the other two processes. In an embodiment of the first process, a two-step electroplating approach is used wherein one of the metals forms the microstructures and the second metal is used as a sacrificial support layer. Following electroplating, the exact height of the microstructures is defined using a chemical mechanical polishing process. In an embodiment of the second process, a modified electroforming process is used for master mold fabrication.
    Type: Application
    Filed: September 22, 2004
    Publication date: March 31, 2005
    Inventors: Chong Ahn, Krishnan Trichur, Sreeram Appasamy