Abstract: A cryogenic system comprising a first cryogenic stage and a second cryogenic stage. A first signal line passing from the first cryogenic stage and is connected to a superconducting thermal break in the second cryogenic stage. A second signal line connecting the superconducting thermal break to a cryogenic device.

Abstract: An organic substrate that has one or more layers. Each of the layers is made of one or more sub-patterns of conductive material disposed on a non-conductive material. The layers are divided into one or more tile subareas. A corresponding layer pair has a corresponding upper layer (with corresponding upper tile subareas) and a corresponding lower layer (with corresponding lower tile subareas) that are equidistant from and symmetric about a reference plane. Each corresponding upper tile subarea and the corresponding lower tile subarea are in a same vertical projection. A symmetric upper (lower) layout on the corresponding upper (lower) tile subarea replaces an original corresponding upper (lower) layer. The symmetric upper and lower layouts have one or more upper portions that have no electrical function but are partly responsible for making the symmetric lower layout and symmetric upper layout more thermo-mechanically symmetric and help reduce warp.

Abstract: Embodiments of a present invention disclose an apparatus including a silicon wafer and a through-silicon-via (TSV) filled with a thermally conductive material located in the silicon wafer, wherein the thermally conductive material has better thermal conduction properties than the silicon wafer when at cryogenic temperatures. A shunt layer connected to the thermal material in the TSV and a heat generating device located directly on top of the thermal material in the TSV and directly on top of the shunt layer, wherein the heat generated by the heat generating device is removed directly by the shunt layer and the thermal material in the TSV.

Abstract: A die stack that includes a first chip die, a second chip die connected to the first chip die by one or more controlled collapse chip connection (“C4”) solder bump bonds, and a spacer die interposed between the first and second chip dies. The spacer die includes through holes for the one or more C4 solder bumps, and has a thickness such that when the first and second chip dies are compressed into contact with the spacer die, the spacer die thickness is a minimum defined spacing between the first and second chip dies, and the spacer die operates as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die.

Abstract: A server node connection system uses two or more proximity sensors per server node to determine progressive, real time changes in wipe length for each individual connector on the node that is connected to an opposing header connector on header connected to a midplane of the server assembly/rack. The system is capable of scanning, monitoring, trending, and alarming.

Abstract: Heat is transferred to a cold plate from one or more subassemblies in an array of subassemblies in an electronic package. The cold plate has a thermally conductive cold plate substrate, a pressure header, a pressure passage, and one or more pressure connections. Each of the pressure connections connects through a housing opening to housing volume defined by a flexible housing in an encapsulated liquid thermal interface (LTI). The flexible housing is in physical and thermal contact with one of the subassemblies through a housing bottom and a top surface of one or more components in the subassembly. A thermally conductive fluid fills the housing volume, housing opening, pressure connections, pressure passage, and pressure header which are all in fluid communication along with one or more other connections, housing openings, and LTIs on other subassemblies. The system transfers heat from the subassemblies to the cold plate while maintaining a constant pressure/stress on each of the subassemblies.

Abstract: The substrate includes one or more bottom circuit (BC) layers disposed one upon another and one or more front circuit (FC) layers disposed one upon another. The FC layers are disposed on the BC layers. In some embodiments, there are one or more core layers disposed between the FC and BC layers. One or more soft zones are located within and penetrate through one or more of the FC layers. Each soft zone has a soft zone volume which is made of one or more component volumes located in each of one or more of the FC layers. Each soft zone component volume has a soft zone cross sectional area. The soft zone cross sectional areas are located inside a chip boundary projection. The chip boundary projection is a vertical projection of one or more sides of a semiconductor chip through the FC layers. The soft zone volume contains a soft zone material with a Young's modulus that is less than 100 GigaPascals (GPa). Alternative embodiments are presented with outside soft zones outside the chip boundary projection.

Abstract: Embodiments of the present invention include an organic substrate that has one or more layers. Each of the layers is made of one or more sub-patterns of conductive material disposed on a non-conductive material. The layers are divided into one or more tile subareas. A corresponding layer pair has a corresponding upper layer (with corresponding upper tile subareas) and a corresponding lower layer (with corresponding lower tile subareas) that are equidistant from and symmetric about a reference plane. Each corresponding upper tile subarea and the corresponding lower tile subarea are in a same vertical projection. Once processed by methods disclosed, a symmetric upper (lower) layout on the corresponding upper (lower) tile subarea replaces an original corresponding upper (lower) layer. The symmetric upper and lower layouts have one or more upper portions that have no electrical function.

Abstract: The substrate includes one or more bottom circuit (BC) layers disposed one upon another and one or more front circuit (FC) layers disposed one upon another. The FC layers are disposed on the BC layers. In some embodiments, there are one or more core layers disposed between the FC and BC layers. One or more soft zones are located within and penetrate through one or more of the FC layers. Each soft zone has a soft zone volume which is made of one or more component volumes located in each of one or more of the FC layers. Each soft zone component volume has a soft zone cross sectional area. The soft zone cross sectional areas are located inside a chip boundary projection. The chip boundary projection is a vertical projection of one or more sides of a semiconductor chip through the FC layers. The soft zone volume contains a soft zone material with a Young's modulus that is less than 100 GigaPascals (GPa). Alternative embodiments are presented with outside soft zones outside the chip boundary projection.

Abstract: Heat is transferred to a cold plate from one or more subassemblies in an array of subassemblies in an electronic package. The cold plate has a thermally conductive cold plate substrate, a pressure header, a pressure passage, and one or more pressure connections. Each of the pressure connections connects through a housing opening to housing volume defined by a flexible housing in an encapsulated liquid thermal interface (LTI). The flexible housing is in physical and thermal contact with one of the subassemblies through a housing bottom and a top surface of one or more components in the subassembly. A thermally conductive fluid fills the housing volume, housing opening, pressure connections, pressure passage, and pressure header which are all in fluid communication along with one or more other connections, housing openings, and LTIs on other subassemblies. The system transfers heat from the subassemblies to the cold plate while maintaining a constant pressure/stress on each of the subassemblies.

Abstract: This invention is a laminated structure and methods used for electrically connecting one or more semiconductor chips to various external electrical connections where stresses within the laminated structure due to thermal cycle are reduced by adding conductive material to selected subareas of upper and lower layers in the structure such that the volume of conductive material in corresponding subareas is equal in amount and orientation within a threshold. This reduces differential stresses between the layers as temperature changes and accordingly reduces failures of materials and/or connections in the structure during manufacturing and operation.

Abstract: A server node connection system uses two or more proximity sensors per server node to determine progressive, real time changes in wipe length for each individual connector on the node that is connected to an opposing header connector on header connected to a midplane of the server assembly/rack. The system is capable of scanning, monitoring, trending, and alarming.

Abstract: A server node connection system uses two or more proximity sensors per server node to determine progressive, real time changes in wipe length for each individual connector on the node that is connected to an opposing header connector on header connected to a midplane of the server assembly/rack. The system is capable of scanning, monitoring, trending, and alarming.

Abstract: A heat spreading lid, including a lid body, a wing portion, where the wing portion flexibly moves independently from the lid body.

Abstract: This invention is a laminated structure and methods used for electrically connecting one or more semiconductor chips to various external electrical connections where stresses within the laminated structure due to thermal cycle are reduced by adding conductive material to selected subareas of upper and lower layers in the structure such that the volume of conductive material in corresponding subareas is equal in amount and orientation within a threshold. This reduces differential stresses between the layers as temperature changes and accordingly reduces failures of materials and/or connections in the structure during manufacturing and operation.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Abstract: A server node connection system uses two or more proximity sensors per server node to determine progressive, real time changes in wipe length for each individual connector on the node that is connected to an opposing header connector on header connected to a midplane of the server assembly/rack. The system is capable of scanning, monitoring, trending, and alarming.

Abstract: This invention is a laminated structure and methods used for electrically connecting one or more semiconductor chips to various external electrical connections where stresses within the laminated structure due to thermal cycle are reduced by adding conductive material to selected subareas of upper and lower layers in the structure such that the volume of conductive material in corresponding subareas is equal in amount and orientation within a threshold. This reduces differential stresses between the layers as temperature changes and accordingly reduces failures of materials and/or connections in the structure during manufacturing and operation.

Abstract: This invention is a laminated structure and methods used for electrically connecting one or more semiconductor chips to various external electrical connections where stresses within the laminated structure due to thermal cycle are reduced by adding conductive material to selected subareas of upper and lower layers in the structure such that the volume of conductive material in corresponding subareas is equal in amount and orientation within a threshold. This reduces differential stresses between the layers as temperature changes and accordingly reduces failures of materials and/or connections in the structure during manufacturing and operation.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.