Patents by Inventor Sri Rama Namala
Sri Rama Namala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11776655Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: GrantFiled: October 13, 2022Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
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Publication number: 20230111510Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: ApplicationFiled: December 6, 2022Publication date: April 13, 2023Inventors: Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee, Chang H. Siau
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Publication number: 20230033870Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: ApplicationFiled: October 13, 2022Publication date: February 2, 2023Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
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Patent number: 11537484Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: GrantFiled: August 6, 2021Date of Patent: December 27, 2022Assignee: Micron Technology, Inc.Inventors: Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee, Chang H. Siau
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Patent number: 11475974Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: GrantFiled: August 4, 2021Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
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Patent number: 11398256Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: GrantFiled: April 9, 2020Date of Patent: July 26, 2022Assignee: Unity Semiconductor CorporationInventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Publication number: 20220199189Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: ApplicationFiled: August 4, 2021Publication date: June 23, 2022Inventors: Sri Rama Namala, Jung Sheng Hoei, Jianmin Huang, Ashutosh Malshe, Xiangang Luo
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Publication number: 20220066894Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: ApplicationFiled: August 6, 2021Publication date: March 3, 2022Inventors: Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee, Chang H. Siau
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Publication number: 20200302973Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: ApplicationFiled: April 9, 2020Publication date: September 24, 2020Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Patent number: 10622028Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: GrantFiled: May 18, 2018Date of Patent: April 14, 2020Assignee: Unity Semiconductor CorporationInventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Patent number: 10552284Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.Type: GrantFiled: April 3, 2017Date of Patent: February 4, 2020Assignee: Western Digital Technologies, Inc.Inventors: Krishanth Skandakumaran, Arun Kumar Medapati, Sri Rama Namala, Ashwin Narasimha, Ajith Kumar B
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Patent number: 10387239Abstract: A computer-implemented method for detecting real flash failures in a runtime environment and determining the cause of the failure may include identifying a software parameter and a hardware parameter associated with a flash memory device at runtime; storing the software parameter and the hardware parameter in a failure detector module coupled to the flash memory device; detecting a flash translation layer failure associated with the flash memory device; performing analysis of the software parameter and the hardware parameter stored in the failure detector module by comparing them to predefined thresholds; and determining a cause of the flash translation layer failure based on the performed analysis.Type: GrantFiled: April 10, 2017Date of Patent: August 20, 2019Assignee: Western Digital Technologies, Inc.Inventors: Sateesh Kondapalli, Sri Rama Namala
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Publication number: 20180342268Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: ApplicationFiled: May 18, 2018Publication date: November 29, 2018Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Publication number: 20180293123Abstract: A computer-implemented method for detecting real flash failures in a runtime environment and determining the cause of the failure may include identifying a software parameter and a hardware parameter associated with a flash memory device at runtime; storing the software parameter and the hardware parameter in a failure detector module coupled to the flash memory device; detecting a flash translation layer failure associated with the flash memory device; performing analysis of the software parameter and the hardware parameter stored in the failure detector module by comparing them to predefined thresholds; and determining a cause of the flash translation layer failure based on the performed analysis.Type: ApplicationFiled: April 10, 2017Publication date: October 11, 2018Inventors: Sateesh Kondapalli, Sri Rama Namala
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Patent number: 10002646Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: GrantFiled: October 29, 2014Date of Patent: June 19, 2018Assignee: Unity Semiconductor CorporationInventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Patent number: 9940036Abstract: Techniques for controlling PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method including monitoring a temperature of a memory attached via the PCIe interface, determining whether an operation implemented on the attached memory has caused the temperature of the memory to exceed a preset threshold, and controlling an I/O rate of the attached memory based on the determination such that the I/O rate is greater than zero.Type: GrantFiled: September 23, 2014Date of Patent: April 10, 2018Assignee: Western Digital Technologies, Inc.Inventors: Krishanth Skandakumaran, Arun Kumar Medapati, Sri Rama Namala, Ashwin Narasimha, Ajith Kumar B
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Publication number: 20170206150Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.Type: ApplicationFiled: April 3, 2017Publication date: July 20, 2017Inventors: Krishanth SKANDAKUMARAN, Arun Kumar MEDAPATI, Sri Rama NAMALA, Ashwin NARASIMHA, Ajith KUMAR B
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Apparatus and methods to control power on PCIe direct attached nonvolatile memory storage subsystems
Patent number: 9612763Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.Type: GrantFiled: September 23, 2014Date of Patent: April 4, 2017Assignee: Western Digital Technologies, Inc.Inventors: Krishanth Skandakumaran, Arun Kumar Medapati, Sri Rama Namala, Ashwin Narasimha, Ajith Kumar B -
Publication number: 20160085458Abstract: Techniques for controlling PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method including monitoring a temperature of a memory attached via the PCIe interface, determining whether an operation implemented on the attached memory has caused the temperature of the memory to exceed a preset threshold, and controlling an I/O rate of the attached memory based on the determination such that the I/O rate is greater than zero.Type: ApplicationFiled: September 23, 2014Publication date: March 24, 2016Applicant: HGST NETHERLANDS B.V.Inventors: Krishanth SKANDAKUMARAN, Arun Kumar MEDAPATI, Sri Rama NAMALA, Ashwin NARASIMHA, Ajith Kumar B
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APPARATUS AND METHODS TO CONTROL POWER ON PCIe DIRECT ATTACHED NONVOLATILE MEMORY STORAGE SUBSYSTEMS
Publication number: 20160085290Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.Type: ApplicationFiled: September 23, 2014Publication date: March 24, 2016Applicant: HGST NETHERLANDS B.V.Inventors: Krishanth SKANDAKUMARAN, Arun Kumar MEDAPATI, Sri Rama NAMALA, Ashwin NARASIMHA, Ajith Kumar B