Patents by Inventor Sri Ranga Sai BOYAPATI
Sri Ranga Sai BOYAPATI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935857Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).Type: GrantFiled: September 23, 2022Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Kristof Darmawaikarta, Robert May, Sashi Kandanur, Sri Ranga Sai Boyapati, Srinivas Pietambaram, Steve Cho, Jung Kyu Han, Thomas Heaton, Ali Lehaf, Ravindranadh Eluri, Hiroki Tanaka, Aleksandar Aleksov, Dilan Seneviratne
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Publication number: 20240088121Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Srinivas PIETAMBARAM, Robert Alan MAY, Kristof DARMAWIKARTA, Hiroki TANAKA, Rahul N. MANEPALLI, Sri Ranga Sai BOYAPATI
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Patent number: 11923307Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: GrantFiled: June 16, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Bai Nie, Gang Duan, Omkar G. Karhade, Nitin A. Deshpande, Yikang Deng, Wei-Lun Jen, Tarek A. Ibrahim, Sri Ranga Sai Boyapati, Robert Alan May, Yosuke Kanaoka, Robin Shea McRee, Rahul N. Manepalli
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Publication number: 20240071777Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Patent number: 11908821Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.Type: GrantFiled: December 28, 2021Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Kristof Darmawikarta, Sri Ranga Sai Boyapati, Hiroki Tanaka, Robert A. May
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Patent number: 11908802Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 16, 2022Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
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Publication number: 20240047229Abstract: A method for forming a core for a substrate that removes portions of a resist layer based on a pattern specifying widths of removed portions of the resist layer. The method forms a set of pillars by plating the remaining portions of the resist layer with a conductive material, so each pillar of the set has a perimeter plated with the conductive material. Additionally, each pillar of the set of pillars is encapsulated with a dielectric material. In some implementations, the dielectric material is an organic material.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: SRI RANGA SAI BOYAPATI, RAJA SWAMINATHAN, DEEPAK VASANT KULKARNI
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Publication number: 20240047228Abstract: A disclosed method can include (i) positioning a first surface of a component of a semiconductor device on a first plated through-hole, (ii) covering, with a layer of dielectric material, at least a second surface of the component that is opposite the first surface of the component, (iii) removing a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity, and (iv) depositing conductive material in the cavity to form a second plated through-hole on the second surface of the component. Various other apparatuses, systems, and methods are also disclosed.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Sri Ranga Sai Boyapati, Deepak Vasant Kulkarni, Raja Swaminathan, Brett P. Wilkerson, Arsalan Alam
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In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same
Patent number: 11894324Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.Type: GrantFiled: November 16, 2021Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Telesphor Kamgaing, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Eyal Fayneh, Ofir Degani, David Levy, Johanna M. Swan -
Patent number: 11894311Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.Type: GrantFiled: April 8, 2022Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Robert Alan May, Islam A. Salama, Sri Ranga Sai Boyapati, Sheng Li, Kristof Darmawikarta, Robert L. Sankman, Amruthavalli Pallavi Alur
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Patent number: 11862619Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.Type: GrantFiled: December 29, 2017Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Srinivas Pietambaram, Robert Alan May, Kristof Darmawikarta, Hiroki Tanaka, Rahul N. Manepalli, Sri Ranga Sai Boyapati
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Publication number: 20230420412Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a package substrate; an interposer coupled to the package substrate, the interposer comprising a dielectric material, a conductive pillar) through the dielectric material and a conductive structure at least partially surrounding the conductive pillar, the conductive structure separated from the conductive pillar by the dielectric material; and an integrated circuit (IC) die coupled to the interposer on a side opposite to the package substrate. The conductive pillar conductively couples the IC die to the package substrate, and the conductive structure is coupled to a ground connection.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Hiroki Tanaka, Kristof Kuwawi Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram
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Patent number: 11854834Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.Type: GrantFiled: February 22, 2022Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Patent number: 11837534Abstract: Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.Type: GrantFiled: December 29, 2017Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Aleksandar Aleksov, Kristof Darmawikarta, Haobo Chen, Changhua Liu, Sri Ranga Sai Boyapati, Bai Nie
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Publication number: 20230326866Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.Type: ApplicationFiled: June 12, 2023Publication date: October 12, 2023Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
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Patent number: 11764158Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.Type: GrantFiled: May 3, 2021Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Amruthavalli Pallavi Alur, Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman
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Patent number: 11735531Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.Type: GrantFiled: July 13, 2021Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Lim
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Patent number: 11699648Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.Type: GrantFiled: March 9, 2022Date of Patent: July 11, 2023Assignee: Tahoe Research, Ltd.Inventors: Srinivas V. Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
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Publication number: 20230140389Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 30, 2022Publication date: May 4, 2023Applicant: Intel CorporationInventors: Aleksandar ALEKSOV, Adel A. ELSHERBINI, Kristof DARMAWIKARTA, Robert A. MAY, Sri Ranga Sai BOYAPATI
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Patent number: 11574874Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.Type: GrantFiled: March 30, 2017Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Robert A. May, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Hiroki Tanaka, Srinivas V. Pietambaram, Frank Truong, Praneeth Akkinepally, Andrew J. Brown, Lauren A. Link, Prithwish Chatterjee