Patents by Inventor SRI SAI SIVAKUMAR VEGUNTA
SRI SAI SIVAKUMAR VEGUNTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11770928Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.Type: GrantFiled: May 10, 2022Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventors: Hongqi Li, James A. Cultra, Sri Sai Sivakumar Vegunta
-
Patent number: 11735473Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.Type: GrantFiled: November 11, 2021Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventors: Jukuan Zheng, Sri Sai Sivakumar Vegunta, Kevin L. Baker, Josiah Jebaraj Johnley Muthuraj, Efe S. Ege
-
Publication number: 20220271052Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.Type: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Inventors: Hongqi Li, James A. Cultra, Sri Sai Sivakumar Vegunta
-
Patent number: 11355508Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.Type: GrantFiled: August 13, 2020Date of Patent: June 7, 2022Assignee: Micron Technology, Inc.Inventors: Hongqi Li, James A. Cultra, Sri Sai Sivakumar Vegunta
-
Publication number: 20220068702Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.Type: ApplicationFiled: November 11, 2021Publication date: March 3, 2022Inventors: Jukuan Zheng, Sri Sai Sivakumar Vegunta, Kevin L. Baker, Josiah Jebaraj Johnley Muthuraj, Efe S. Ege
-
Publication number: 20220052061Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.Type: ApplicationFiled: August 13, 2020Publication date: February 17, 2022Inventors: Hongqi Li, James A. Cultra, Sri Sai Sivakumar Vegunta
-
Patent number: 11201083Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.Type: GrantFiled: February 3, 2020Date of Patent: December 14, 2021Assignee: Micron Technology, Inc.Inventors: Jukuan Zheng, Sri Sai Sivakumar Vegunta, Kevin L. Baker, Josiah Jebaraj Johnley Muthuraj, Efe S. Ege
-
Patent number: 11088017Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.Type: GrantFiled: March 2, 2020Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
-
Publication number: 20210202299Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.Type: ApplicationFiled: February 3, 2020Publication date: July 1, 2021Inventors: Jukuan Zheng, Sri Sai Sivakumar Vegunta, Kevin L. Baker, Josiah Jebaraj Johnley Muthuraj, Efe S. Ege
-
Patent number: 11010058Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.Type: GrantFiled: June 11, 2019Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Jun Zhao, Gowrisankar Damaria, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
-
Publication number: 20200203220Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
-
Patent number: 10600682Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.Type: GrantFiled: October 26, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
-
Publication number: 20190294330Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Applicant: Intel CorporationInventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
-
Publication number: 20190206727Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.Type: ApplicationFiled: October 26, 2018Publication date: July 4, 2019Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
-
Patent number: 10318170Abstract: Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.Type: GrantFiled: January 2, 2018Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
-
Patent number: 10269625Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.Type: GrantFiled: December 28, 2017Date of Patent: April 23, 2019Assignee: Micron Technology, Inc.Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
-
Publication number: 20190051662Abstract: A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.Type: ApplicationFiled: October 5, 2018Publication date: February 14, 2019Inventors: Sri Sai Sivakumar VEGUNTA, Gowrisankar DAMARLA, Jian ZHOU
-
Publication number: 20180307412Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.Type: ApplicationFiled: January 2, 2018Publication date: October 25, 2018Applicant: Intel CorporationInventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
-
Patent number: 10096612Abstract: A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.Type: GrantFiled: September 14, 2015Date of Patent: October 9, 2018Assignee: Intel CorporationInventors: Sri Sai Sivakumar Vegunta, Gowrisankar Damarla, Jian Zhou
-
Patent number: 9857989Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.Type: GrantFiled: October 1, 2016Date of Patent: January 2, 2018Assignee: Intel CorporationInventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau