Patents by Inventor Srihari Makineni
Srihari Makineni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111531Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.Type: ApplicationFiled: September 15, 2023Publication date: April 4, 2024Inventors: Stephen T. PALERMO, Srihari MAKINENI, Shubha BOMMALINGAIAHNAPALLYA, Neelam CHANDWANI, Rany T. ELSAYED, Udayan MUKHERJEE, Lokpraveen MOSUR, Adwait PURANDARE
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Patent number: 11775298Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.Type: GrantFiled: July 20, 2020Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Stephen T. Palermo, Srihari Makineni, Shubha Bommalingaiahnapallya, Neelam Chandwani, Rany T. Elsayed, Udayan Mukherjee, Lokpraveen Mosur, Adwait Purandare
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Publication number: 20230217253Abstract: Systems, methods, and apparatus for workload optimized central processing units are disclosed herein. An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.Type: ApplicationFiled: March 26, 2021Publication date: July 6, 2023Inventors: Stephen Palermo, Srihari Makineni, Shubha Bommalingaiahnapallya, Rany ElSayed, Lokpraveen Mosur, Neelam Chandwani, Pinkesh Shah, Rajesh Gadiyar, Shrikant M. Shah, Uzair Qureshi
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Patent number: 11567556Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).Type: GrantFiled: March 27, 2020Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Chris Macnamara, John J. Browne, Tomasz Kantecki, David Hunt, Anatoly Burakov, Srihari Makineni, Nikhil Gupta, Ankush Varma, Dorit Shapira, Vasudevan Srinivasan, Bryan T. Butters, Shrikant M. Shah
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Publication number: 20210334101Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.Type: ApplicationFiled: July 20, 2020Publication date: October 28, 2021Inventors: Stephen T. Palermo, Srihari Makineni, Shubha Bommalingaiahnapallya, Neelam Chandwani, Rany T. Elsayed, Udayan Mukherjee, Lokpraveen Mosur, Adwait Purandare
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Publication number: 20200328973Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: May 10, 2020Publication date: October 15, 2020Applicant: Intel CorporationInventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20200225724Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Chris MACNAMARA, John J. BROWNE, Tomasz KANTECKI, David HUNT, Anatoly BURAKOV, Srihari MAKINENI, Nikhil GUPTA, Ankush VARMA, Dorit SHAPIRA, Vasudevan SRINIVASAN, Bryan T. BUTTERS, Shrikant M. SHAH
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Patent number: 10664039Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: GrantFiled: July 24, 2018Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
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Patent number: 10652147Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: GrantFiled: December 29, 2017Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20180329478Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
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Patent number: 10095520Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.Type: GrantFiled: June 27, 2016Date of Patent: October 9, 2018Assignee: Intel CorporationInventors: Zhen Fang, Xiaowei Jiang, Srihari Makineni, Rameshkumar G. Illikkal, Ravishankar Iyer
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Patent number: 10048743Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: GrantFiled: April 21, 2016Date of Patent: August 14, 2018Assignee: Intel CorporationInventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
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Publication number: 20180198709Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: December 29, 2017Publication date: July 12, 2018Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 9870047Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: GrantFiled: June 24, 2016Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
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Patent number: 9864427Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: GrantFiled: April 21, 2016Date of Patent: January 9, 2018Assignee: Intel CorporationInventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
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Patent number: 9753732Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.Type: GrantFiled: June 7, 2016Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
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Publication number: 20170048142Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: October 31, 2016Publication date: February 16, 2017Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20160306415Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
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Publication number: 20160306630Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: ZHEN FANG, XIAOWEI JIANG, SRIHARI MAKINENI, RAMESHKUMAR G. ILLIKKAL, RAVISHANKAR IYER
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Publication number: 20160299558Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.Type: ApplicationFiled: April 21, 2016Publication date: October 13, 2016Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadogopan Srinivasan, Jaideep Moses, Srihari Makineni