Abstract: A method includes comparing a voltage level detected by a detection circuit to a set of threshold voltages to determine a type of a headphone, determining the headphone to be a first type when a first signal travels through the first path to ground, and determining the headphone to be a second type when a second signal travels through the second path. The detection circuit includes a first path, a second path, and a bias capacitor. The headphone of the second type includes a plug that has a microphone connection.

Abstract: Aspects of the disclosure provide an audio circuit that includes a clock circuit, a transmitting circuit, an audio data preparation circuit and a controller. The controller is configured to provide control signals to configure the transmitting circuit and the audio data preparation circuit according to one of a plurality of link protocol. The clock circuit is configured to provide a clock signal for bit transmission. The transmitting circuit is configured to transmit a bit in response to a transition edge of the clock signal according to the link protocol. The audio data preparation circuit is configured to insert audio data into a bit stream and provide the bit stream to the transmitting circuit according to the link protocol.

Abstract: A method includes detecting insertion of a headphone into an electronic device, comparing a voltage level detected by a detection circuit of the electronic device to a set of threshold voltages to determine a type of the headphone, determining the headphone to be a first type when a first signal travels through the first path to ground, and determining the headphone to be a second type when a second signal travels through the second path to charge the bias capacitor to a reference voltage. The detection circuit includes a first path, a second path, and a bias capacitor.

Abstract: A system including a first circuit, a second circuit, an amplifier, and a summer. The first circuit is configured to (i) select a first portion of a signal, and (ii) generate a first compensation for asymmetry in the first portion of the signal using a first function, where the first function is a modulus function. The second circuit is configured to (i) select a second portion of the signal, and (ii) generate a second compensation for asymmetry in the second portion of the signal using a second function, where the second function is different than the first function. The amplifier amplifies the signal and provides an amplified output. The summer is configured to add (i) the first compensation, (ii) the second compensation, and (iii) the amplified output, where (i) the first circuit, (ii) the second circuit, and (iii) the amplifier are connected in parallel to the summer.

Abstract: Aspects of the disclosure provide an audio circuit that includes a clock circuit, a transmitting circuit, an audio data preparation circuit and a controller. The controller is configured to provide control signals to configure the transmitting circuit and the audio data preparation circuit according to one of a plurality of link protocol. The clock circuit is configured to provide a clock signal for bit transmission. The transmitting circuit is configured to transmit a bit in response to a transition edge of the clock signal according to the link protocol. The audio data preparation circuit is configured to insert audio data into a bit stream and provide the bit stream to the transmitting circuit according to the link protocol.

Abstract: To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.

Abstract: A system including a first circuit and a second circuit. The first circuit is configured to (i) select a first portion of a signal based on a first offset, (ii) amplify the first portion of the signal according to a first function, and (iii) scale the amplified first portion based on a first factor to generate a first compensation for asymmetry in the first portion of the signal. The second circuit is configured to (i) select a second portion of the signal based on a second offset, (ii) amplify the second portion according to a second function, and (iii) scale the amplified second portion based on a second factor to generate a second compensation for asymmetry in the second portion of the signal.

Abstract: A circuit for compensating asymmetry in a waveform of an input signal using a piecewise approximation of a saturation curve, the circuit including a first circuit configured to output a first compensation for a first section of the saturation curve using a first function and a second circuit configured to output a second compensation for a second section of the saturation curve using a second function. The second function is different than the first function. The first compensation and the second compensation provide the piecewise approximation of a region of the saturation curve. The region includes at least the first second and the second section.

Abstract: To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.

Abstract: A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).

Abstract: A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).