Abstract: A moving window history of at least one previous data address accessed by a processor is maintained, the at least one previous data address in the history each being associated with an index. A difference between a current data address and one of the at least one previous data address in the history is determined. The difference and the index associated with the one of the at least one previous data address in the history are provided as a representation of the current address.

Abstract: A moving window history of at least one previous data address accessed by a processor is maintained, the at least one previous data address in the history each being associated with an index. A difference between a current data address and one of the at least one previous data address in the history is determined. The difference and the index associated with the one of the at least one previous data address in the history are provided as a representation of the current address.

Abstract: Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array, storing in a selected entry in the tag array information representative of a branch target of a current branch instruction, storing in a corresponding entry in the data array information representative of a branch target of a next branch instruction, and providing the information representative of the branch target of the next branch instruction in response to a match to an entry in the tag array. The information representative of the branch target of the next branch instruction may include a taken branch target address of the next branch instruction and an offset value. The offset value may represent an address of a next sequential instruction following the next branch instruction.

Abstract: An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer.

Abstract: Methods and apparatus are provided for issuing instructions in a processor having a pipeline. A method includes providing a loop buffer for holding program loop instructions and a register file for holding loop control parameters; in response to decoding of a first loop setup instruction, marking a first entry in the register file as a current entry and writing in the first entry loop control parameters represented in the first loop setup instruction; marking the current entry in the register file as an architectural entry in response to the first loop setup instruction being committed; and sending a loop bottom indicator down the pipeline with a loop bottom instruction.

Abstract: An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer.

Abstract: Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array, storing in a selected entry in the tag array information representative of a branch target of a current branch instruction, storing in a corresponding entry in the data array information representative of a branch target of a next branch instruction, and providing the information representative of the branch target of the next branch instruction in response to a match to an entry in the tag array. The information representative of the branch target of the next branch instruction may include a taken branch target address of the next branch instruction and an offset value. The offset value may represent an address of a next sequential instruction following the next branch instruction.