Patents by Inventor Srikanth Krishnan
Srikanth Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092778Abstract: The present disclosure relates to a topical pharmaceutical composition containing N-[(1S)-1-(5-fluoropyrimidin-2-yl)ethyl]-3-(5-isopropoxy-1H-pyrazol-3-yl)-3H-imidazo[4,5-b]pyridin-5-amine (hereinafter also referred to as “Compound A”), or a pharmaceutically acceptable salt thereof; to the use of the topical pharmaceutical composition as a medicament; to processes for the preparation of said topical pharmaceutical composition; to certain new methods of treating an inflammatory skin disorder, particularly psoriasis, by administering a topical pharmaceutical composition containing Compound A or a pharmaceutically acceptable salt thereof; and to novel crystalline forms of a mesylate salt of Compound A.Type: ApplicationFiled: December 28, 2021Publication date: March 21, 2024Inventors: Kollol PAL, Abhijit BHAT, Jay BIRNBAUM, Vijendra NALAMOTHU, Srikanth MANNE, Gayathri KRISHNAN, Jean-Philippe THERRIEN
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Publication number: 20230061337Abstract: An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Jungwoo Joh, Sunglyong Kim, Seetharaman Sridhar, Sameer Pendharkar, James Craig Ondrusek, Srikanth Krishnan
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Patent number: 9476933Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.Type: GrantFiled: November 19, 2014Date of Patent: October 25, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jungwoo Joh, Srikanth Krishnan, Sameer Pendharkar
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Publication number: 20150160285Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.Type: ApplicationFiled: November 19, 2014Publication date: June 11, 2015Inventors: Jungwoo Joh, Srikanth Krishnan, Sameer Pendharkar
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Patent number: 8219953Abstract: Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.Type: GrantFiled: January 18, 2009Date of Patent: July 10, 2012Assignee: Texas Instruments IncorporatedInventors: Palkesh Jain, Young-Joon Park, Srikanth Krishnan, Guru Chakrapani Prasad
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Patent number: 8138829Abstract: Various apparatuses and methods for varying segment activation in a segmented power amplifier are disclosed herein. For example, some embodiments provide a power amplifier including an input, an output, a plurality of amplifier segments and a controller. The amplifier segments are connected in parallel between the input and the output and are adapted to be activated and inactivated. The power level at the output may be controlled by changing a number of the amplifier segments that are activated concurrently. The controller is connected to the amplifier segments and is adapted to vary which of the amplifier segments are activated to arrive at a selected number of activated amplifier segments.Type: GrantFiled: May 27, 2010Date of Patent: March 20, 2012Assignee: Texas Instruments IncorporatedInventors: Vijay Kumar Reddy, Srikanth Krishnan, Brian P Ginsburg, Srinath Mathur Ramaswamy, Chih-Ming Hung
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Publication number: 20110291754Abstract: Various apparatuses and methods for varying segment activation in a segmented power amplifier are disclosed herein. For example, some embodiments provide a power amplifier including an input, an output, a plurality of amplifier segments and a controller. The amplifier segments are connected in parallel between the input and the output and are adapted to be activated and inactivated. The power level at the output may be controlled by changing a number of the amplifier segments that are activated concurrently. The controller is connected to the amplifier segments and is adapted to vary which of the amplifier segments are activated to arrive at a selected number of activated amplifier segments.Type: ApplicationFiled: May 27, 2010Publication date: December 1, 2011Inventors: Vijay Kumar Reddy, Srikanth Krishnan, Brian P. Ginsburg, Srinath Mathur Ramaswamy, Chih-Ming Hung
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Patent number: 7974595Abstract: One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.Type: GrantFiled: January 11, 2008Date of Patent: July 5, 2011Assignee: Texas Instruments IncorporatedInventors: Vijay Kumar Reddy, Andrew Marshall, Siraj Akhtar, Srikanth Krishnan, Karan Singh Bhatia
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Patent number: 7808266Abstract: Apparatus and methods are disclosed for evaluating degradation of a transistor in a cross coupled pair of an RF oscillator independently. A MOS device can be coupled between a separated center-tap inductor. By appropriately sizing the MOS device and turning the MOS device on during operation of RF oscillator, a good contact can again be made that allows the oscillator to operate at design performance. By turning the MOS device off, the supplies can be separates such that I-V characteristics of both transistors of the cross-coupled pair may be obtained.Type: GrantFiled: January 13, 2009Date of Patent: October 5, 2010Assignee: Texas Instruments IncorporatedInventors: Andrew Marsall, Srikanth Krishnan
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Patent number: 7750400Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).Type: GrantFiled: August 15, 2008Date of Patent: July 6, 2010Assignee: Texas Instruments IncorporatedInventors: Ajit Shanware, Srikanth Krishnan
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Publication number: 20100164533Abstract: Apparatus and methods are disclosed for evaluating degradation of a transistor in a cross coupled pair of an RF oscillator independently. A MOS device can be coupled between a separated center-tap inductor. By appropriately sizing the MOS device and turning the MOS device on during operation of RF oscillator, a good contact can again be made that allows the oscillator to operate at design performance. By turning the MOS device off, the supplies can be separates such that I-V characteristics of both transistors of the cross-coupled pair may be obtained.Type: ApplicationFiled: January 13, 2009Publication date: July 1, 2010Applicant: Texas Instruments IncorporatedInventors: Andrew Marshall, Srikanth Krishnan
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Publication number: 20100038683Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).Type: ApplicationFiled: August 15, 2008Publication date: February 18, 2010Inventors: Ajit Shanware, Srikanth Krishnan
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Patent number: 7638412Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: GrantFiled: July 24, 2007Date of Patent: December 29, 2009Assignee: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
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Publication number: 20090187869Abstract: Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.Type: ApplicationFiled: January 18, 2009Publication date: July 23, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Palkesh Jain, Young-Joon Park, Srikanth Krishnan, Guruprasad C
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Publication number: 20090167429Abstract: One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.Type: ApplicationFiled: January 11, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Vijay Kumar Reddy, Andrew Marshall, Siraj Akhtar, Srikanth Krishnan, Karan Singh Bhatia
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Publication number: 20070264804Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: ApplicationFiled: July 24, 2007Publication date: November 15, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Gallia, Srikanth Krishnan, Anand Krishnan
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Patent number: 7262468Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: GrantFiled: December 28, 2001Date of Patent: August 28, 2007Assignee: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
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Patent number: 7218132Abstract: Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.Type: GrantFiled: November 30, 2005Date of Patent: May 15, 2007Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Srikanth Krishnan, Vijay Reddy, Cathy Chancellor
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Patent number: 7212023Abstract: Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.Type: GrantFiled: September 7, 2004Date of Patent: May 1, 2007Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Srikanth Krishnan, Vijay Reddy, Cathy Chancellor
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Patent number: 7122466Abstract: An embodiment of the invention is a method of manufacturing copper interconnects 30 on a semiconductor wafer 10 where an electroplating process is used to deposit a first layer of copper grains 30d having an initial grain size and a second layer of copper grains 30e having a different initial grain size.Type: GrantFiled: July 28, 2003Date of Patent: October 17, 2006Assignee: Texas Instruments IncorporatedInventors: Young-Joon Park, Srikanth Krishnan