Patents by Inventor Srikar Peesari
Srikar Peesari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11023327Abstract: A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.Type: GrantFiled: March 20, 2018Date of Patent: June 1, 2021Assignee: Western Digital Technologies, Inc.Inventors: Daniel Joseph Linnen, Ashish Ghai, Avinash Rajagiri, Srikar Peesari
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Patent number: 10886002Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.Type: GrantFiled: June 13, 2019Date of Patent: January 5, 2021Assignee: SanDisk Technologies LLCInventors: Daniel Linnen, Avinash Rajagiri, Yuvaraj Krishnamoorthy, Srikar Peesari, Ashish Ghai, Dongxiang Liao
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Publication number: 20200395092Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.Type: ApplicationFiled: June 13, 2019Publication date: December 17, 2020Applicant: SanDisk Technologies LLCInventors: Dan Linnen, Avi Rajagiri, Yuvaraj Krishnamoorthy, Srikar Peesari, Ashish Ghai, Dongxiang Liao
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Patent number: 10846418Abstract: A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.Type: GrantFiled: December 20, 2017Date of Patent: November 24, 2020Assignee: Western Digital Technologies, Inc.Inventors: Daniel Joseph Linnen, Avinash Rajagiri, Srikar Peesari, Ashish Ghai, Dongxiang Liao, Rohit Sehgal
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Patent number: 10776277Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.Type: GrantFiled: October 31, 2017Date of Patent: September 15, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj
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Publication number: 20190294507Abstract: A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.Type: ApplicationFiled: March 20, 2018Publication date: September 26, 2019Applicants: Western Digital Technologies, Inc., Western Digital Technologies, Inc.Inventors: Daniel Joseph Linnen, Ashish Ghai, Avinash Rajagiri, Srikar Peesari
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Publication number: 20190188403Abstract: A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.Type: ApplicationFiled: December 20, 2017Publication date: June 20, 2019Inventors: Daniel Joseph Linnen, Avinash Rajagiri, Srikar Peesari, Ashish Ghai, Dongxiang Liao, Rohit Sehgal
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Publication number: 20190187553Abstract: An apparatus is provided that includes a reticle including a die, the reticle configured to increase a number of partial die that can be successfully used as partially operable die.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Applicant: SANDISK TECHNOLOGIES LLCInventors: Daniel J. Linnen, Jianhua Zhu, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj
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Patent number: 10324859Abstract: Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.Type: GrantFiled: June 26, 2017Date of Patent: June 18, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Daniel Joseph Linnen, Ashish Ghai, Dongxiang Liao, Srikar Peesari, Avinash Rajagiri, Philip Reusswig, Bin Wu
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Patent number: 10290354Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.Type: GrantFiled: October 31, 2017Date of Patent: May 14, 2019Assignee: SanDisk Technologies LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj, Sukhminder Singh Lobana, Shrikar Bhagath
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Publication number: 20190130978Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: SANDISK TECHNOLOGIES LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj, Sukhminder Singh Lobana, Shrikar Bhagath
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Publication number: 20190129861Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: SANDISK TECHNOLOGIES LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj
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Patent number: 10242750Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.Type: GrantFiled: May 31, 2017Date of Patent: March 26, 2019Assignee: SanDisk Technologies LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Shantanu Gupta, Avinash Rajagiri, Dongxiang Liao, Jagdish Sabde, Rajan Paudel
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Publication number: 20180373644Abstract: Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.Type: ApplicationFiled: June 26, 2017Publication date: December 27, 2018Applicant: Western Digital Technologies, Inc.Inventors: Daniel Joseph Linnen, Ashish Ghai, Dongxiang Liao, Srikar Peesari, Avinash Rajagiri, Philip Reusswig, Bin Wu
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Publication number: 20180350445Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Shantanu Gupta, Avinash Rajagiri, Dongxiang Liao, Jagdish Sabde, Rajan Paudel
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Patent number: 9711227Abstract: To prevent data loss due to latent defects, a non-volatile memory system will use a leakage detection circuit to test for small amounts of leakage that indicate that the memory is susceptible to failure.Type: GrantFiled: April 28, 2016Date of Patent: July 18, 2017Assignee: SanDisk Technologies LLCInventors: Ashish Ghai, Yuvaraj Krishnamoorthy, Ekamdeep Singh, Kalpana Vakati, Maythin Uthayopas, Mark Shlick, Srikar Peesari