Patents by Inventor Srinadh Madhavapeddi
Srinadh Madhavapeddi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11341015Abstract: A system includes a battery and a monitoring circuit coupled to the battery. The monitoring circuit includes a sense circuit and a peripheral device coupled to the sense circuit. The peripheral device includes a universal asynchronous receiver-transmitter (UART) receiver having an adaptive sample timing circuit with a numerically-controlled oscillator (NCO) circuit. The peripheral device also includes memory coupled to the UART receiver and configured to store battery monitoring data.Type: GrantFiled: September 30, 2019Date of Patent: May 24, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Timothy Murphy, Srinadh Madhavapeddi, Terry Lee Sculley
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Publication number: 20210096969Abstract: A system includes a battery and a monitoring circuit coupled to the battery. The monitoring circuit includes a sense circuit and a peripheral device coupled to the sense circuit. The peripheral device includes a universal asynchronous receiver-transmitter (UART) receiver having an adaptive sample timing circuit with a numerically-controlled oscillator (NCO) circuit. The peripheral device also includes memory coupled to the UART receiver and configured to store battery monitoring data.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: Timothy MURPHY, Srinadh MADHAVAPEDDI, Terry Lee SCULLEY
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Patent number: 10536258Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.Type: GrantFiled: June 2, 2018Date of Patent: January 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hunsoo Choo, Hamid Safiri, Nikolaus Klemmer, Jaimin Mehta, Srinadh Madhavapeddi, Charles Kasimer Sestok, Vijayavardhan Baireddy
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Publication number: 20190372747Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.Type: ApplicationFiled: June 2, 2018Publication date: December 5, 2019Inventors: Hunsoo Choo, Hamid Safiri, Nikolaus Klemmer, Jaimin Mehta, Srinadh Madhavapeddi, Charles Kasimer Sestok, Vijayavardhan Baireddy
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Patent number: 10218338Abstract: Aperiodic clock generation with clock spur suppression is based on cascaded randomizers, such as for mixed signal devices. A clock generator circuit includes an input node to receive the input periodic clock signal having an input-clock frequency. A first randomizer circuit coupled to receive the input clock signal from the input node, to perform signal randomization to suppress spurious signal content associated with (a) the input clock signal, and (b) the first randomizer circuit, and to generate an intermediate clock signal. A second concatenated randomizer circuit is coupled to receive the intermediate clock signal, to perform signal randomization to suppress spurious signal content associated with (a) the intermediated clock signal, and (b) the second randomizer circuit, and to generate an aperiodic output clock signal having a pre-defined average output-clock frequency that is less than the input-clock frequency. Example randomizers are a delta-sigma divider and a pulse swallower (in any order).Type: GrantFiled: October 12, 2017Date of Patent: February 26, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nikolaus Klemmer, Chan Fernando, Jaimin Mehta, Srinadh Madhavapeddi, Hamid Safiri, Atul Kumar Jain
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Patent number: 9342482Abstract: A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.Type: GrantFiled: November 12, 2012Date of Patent: May 17, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joonsung Park, Srinadh Madhavapeddi, Christopher Barr
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Publication number: 20140136138Abstract: A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.Type: ApplicationFiled: November 12, 2012Publication date: May 15, 2014Applicant: Texas Instruments, IncorporatedInventors: Joonsung Park, Srinadh Madhavapeddi, Christopher Barr
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Patent number: 8022778Abstract: Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.Type: GrantFiled: October 10, 2009Date of Patent: September 20, 2011Assignee: Texas Instruments IncorporatedInventors: Krishnasawamy Nagaraj, Neeraj Nayak, Srinadh Madhavapeddi, Baher Haroun
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Publication number: 20110084771Abstract: Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.Type: ApplicationFiled: October 10, 2009Publication date: April 14, 2011Inventors: Krishnasawamy Nagaraj, Neeraj Nayak, Srinadh Madhavapeddi, Baher Haroun
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Patent number: 7877536Abstract: A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.Type: GrantFiled: December 26, 2007Date of Patent: January 25, 2011Assignee: Texas Instruments IncorporatedInventors: Roy D. Wojciechowski, Srinadh Madhavapeddi, Scott Adam Morrison, Pradip Thaker
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Publication number: 20090172237Abstract: A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.Type: ApplicationFiled: December 26, 2007Publication date: July 2, 2009Inventors: Roy D. Wojciechowski, Srinadh Madhavapeddi, Scott Adam Morrison
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Patent number: 7304977Abstract: A sequence of data samples and a sequence of non-data samples are provided. Four input samples from one of the data samples and the non-data samples are selected based on a clock signal. At least a portion of contents of a first group of memory cells are stored in a second group of memory cells. The first group of memory cells are comprised of four memory cells. The selected four input samples are stored in the first group of memory cells.Type: GrantFiled: January 14, 2005Date of Patent: December 4, 2007Assignee: Texas Instruments IncorporatedInventors: Navin S. Chander, Srinadh Madhavapeddi, Mitsuru Shimada, Srinivas Lingam
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Publication number: 20060224651Abstract: A system (12) for determining discrete transforms as between time and frequency domains. The system comprises a grid (60) comprising adders and multipliers. The grid is operable to perform in parallel an integer number P operations of a first transform function selected from one of either an IFFT or an FFT. The system also comprises the integer number of P serially-operating pipelines (641-648). Each of the pipelines is coupled to the grid and is operable to perform serially over a number of cycles an integer number S operations of the first transform. In the system, S and P are both greater than one and, in combination, the grid and the serially-operating pipelines perform the first transform type as an S×P-point transform. In a first instance at least a portion of the grid is operable to perform IFFT operations. In a second instance at least a portion of the grid is operable to perform FFT operations.Type: ApplicationFiled: March 31, 2005Publication date: October 5, 2006Applicant: Texas Instruments IncorporatedInventors: Srinadh Madhavapeddi, Manish Goel, Henry Angulo
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Publication number: 20050180376Abstract: A system and method is provided for processing four samples per clock period of an orthogonal frequency division multiplex symbol 10 having a length not a multiple of four. The method includes providing a sequence of data samples 12 and a sequence of non-data samples 14 and 16. The method includes selecting four input samples from one of the data samples 12 and the non-data samples 14 and 16 based on a clock signal. The method includes storing at least a portion of contents of a first group of memory cells 112 in a second group of memory cells 116. The first group of memory cells 112 comprised of four memory cells 112a-d. The method also provides for storing the selected four input samples in the first group of memory cells 112.Type: ApplicationFiled: January 14, 2005Publication date: August 18, 2005Applicant: Texas Instruments IncorporatedInventors: Navin Chander, Srinadh Madhavapeddi, Mitsuru Shimada, Srinivas Lingam