Patents by Inventor Srinivas Gandikota
Srinivas Gandikota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817320Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.Type: GrantFiled: August 29, 2019Date of Patent: November 14, 2023Assignee: Applied Materials, Inc.Inventors: Susmit Singha Roy, Kelvin Chan, Hien Minh Le, Sanjay Kamath, Abhijit Basu Mallick, Srinivas Gandikota, Karthik Janakiraman
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Publication number: 20230323543Abstract: Embodiments of the disclosure advantageously provide in situ selectively deposited molybdenum films having reduced resistivity and methods of reducing or eliminating lateral growth of a selectively deposited molybdenum layer. Additional embodiments provide integrated clean and deposition processes which improve the selectivity of in situ selectively deposited molybdenum films on features, such as a via. Further embodiments advantageously provide methods of improving uniformity and selectivity of bottom-up gap fill for vias with improved film properties.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Applicant: Applied Materials, Inc.Inventors: Tuerxun Ailihumaer, Yixiong Yang, Annamalai Lakshmanan, Srinivas Gandikota, Yogesh Sharma, Pei Hsuan Lin, Yi Xu, Zhimin Qi, Aixi Zhang, Shiyu Yue, Yu Lei
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Publication number: 20230326744Abstract: Embodiments of the disclosure relate to methods for bottom-up metal gapfill without substantial deposition outside of the feature. Additional embodiments provide a method of forming a metal material on the top surface of the substrate and the bottom of the feature before depositing the metal gapfill.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Applicant: Applied Materials, Inc.Inventors: Annamalai Lakshmanan, Yixiong Yang, Srinivas Gandikota, Joung Joo Lee, Liqi Wu, Jie Zhang, Tuerxun Ailihumaer, Yogesh Sharma
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Patent number: 11776980Abstract: Methods and apparatus for forming reflector films are described A liner is formed on a substrate surface followed by formation of the reflector layer so that there is no oxygen exposure between liner and reflector layer formation. In some embodiments, a high aspect ratio structure is filled with a reflector material by partially filling the structure with the reflector material while growth is inhibited at a top portion of the structure, reactivating the top portion of the substrate and then filling the structure with the reflector material.Type: GrantFiled: March 13, 2020Date of Patent: October 3, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Luping Li, Jacqueline S. Wrench, Wen Ting Chen, Yixiong Yang, In Seok Hwang, Shih Chung Chen, Srinivas Gandikota
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Publication number: 20230295804Abstract: Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X?, and Y? are independently selected from nitrogen (N) and carbon (C).Type: ApplicationFiled: May 2, 2023Publication date: September 21, 2023Applicant: Applied Materials, Inc.Inventors: Srinivas Gandikota, Geetika Bajaj, Yixiong Yang, Seshadri Ganguli, Tuerxun Ailihumaer, Yogesh Sharma, Tianyi Huang
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Patent number: 11732358Abstract: Process chamber lids, processing chambers and methods using the lids are described. The lid includes a pumping liner with a showerhead, blocker plate and gas funnel positioned therein. A liner heater is positioned on the pumping liner to control temperature in the pumping liner. Gas is flowed into the gas funnel using a dead-volume free one-way valve with a remote plasma source.Type: GrantFiled: August 17, 2022Date of Patent: August 22, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Muhannad Mustafa, Muhammad M. Rasheed, Mario D. Sanchez, Srinivas Gandikota, Wei V. Tang
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Publication number: 20230260791Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-? dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-? dielectric layer on the interfacial layer, and a metal film on the high-? dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-? dielectric layer.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Applicant: Applied Materials, Inc.Inventors: Srinivas Gandikota, Yixiong Yang, Steven C.H. Hung, Tianyi Huang, Seshadri Ganguli
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Publication number: 20230253466Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAIN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAIC).Type: ApplicationFiled: April 3, 2023Publication date: August 10, 2023Applicant: Applied Materials, Inc.Inventors: Yongjing Lin, Karla M Bernal Ramos, Shih Chung Chen, Yixiong Yang, Lin Dong, Steven C.H. Hung, Srinivas Gandikota
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Publication number: 20230245925Abstract: A method for forming a metal nitride layer on a substrate includes exposing a substrate having features formed therein to a first deposition gas mixture including metal source material in a processing chamber to deposit metal source material in the features, supplying a first purge gas mixture into the processing chamber to remove excess metal source material and reaction byproducts from the processing chamber, exposing the substrate to a second deposition gas mixture including a nitride source compound in the processing chamber to form no more than one monolayer of metal nitride, supplying a second purge gas mixture into the processing chamber to remove excess nitride source compound and reaction byproducts from the processing chamber, and exposing the substrate to plasma using a microwave plasma source.Type: ApplicationFiled: March 24, 2023Publication date: August 3, 2023Inventors: Wenyi LIU, Wei TANG, Srinivas GANDIKOTA, Yixiong YANG, Yong WU, Jianqiu GUO, Arkaprava DAN, Mandyam SRIRAM
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Patent number: 11705335Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.Type: GrantFiled: April 20, 2022Date of Patent: July 18, 2023Assignee: Applied Materials, Inc.Inventors: Srinivas Gandikota, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy, Gaurav Thareja, Mukund Srinivasan, Sanjay Natarajan
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Patent number: 11658218Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).Type: GrantFiled: February 10, 2022Date of Patent: May 23, 2023Assignee: Applied Materials, Inc.Inventors: Yongjing Lin, Karla M Bernal Ramos, Shih Chung Chen, Yixiong Yang, Lin Dong, Steven C. H. Hung, Srinivas Gandikota
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Publication number: 20230154726Abstract: Embodiments described herein relate to magnetic and electromagnetic systems and a method for controlling the density profile of plasma generated in a process volume of a PECVD chamber to affect deposition profile of a film. In one embodiment, a plurality of retaining brackets is disposed in a rotational magnetic housing of the magnetic housing systems. Each retaining bracket of the plurality of retaining brackets is disposed in the rotational magnetic housing with a distance d between each retaining bracket. The plurality of retaining brackets has a plurality of magnets removably disposed therein. The plurality of magnets is configured to travel in a circular path when the rotational magnetic housing is rotated around the round central opening.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Inventors: Srinivas GANDIKOTA, Tza-Jing GUNG, Samuel E. GOTTHEIM, Timothy Joseph FRANKLIN, Pramit MANNA, Eswaranand VENKATASUBRAMANIAN, Edward HAYWOOD, Stephen C. GARNER, Adam FISCHBACH
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Publication number: 20230141748Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.Type: ApplicationFiled: January 3, 2023Publication date: May 11, 2023Applicant: Applied Materials, Inc.Inventors: Yixiong Yang, Jacqueline S. Wrench, Yong Yang, Srinivas Gandikota, Annamalai Lakshmanan, Joung Joo Lee, Feihu Wang, Seshadri Ganguli
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Patent number: 11646226Abstract: A method for forming a metal nitride layer on a substrate includes exposing a substrate having features formed therein to a first deposition gas mixture including metal source material in a processing chamber to deposit metal source material in the features, supplying a first purge gas mixture into the processing chamber to remove excess metal source material and reaction byproducts from the processing chamber, exposing the substrate to a second deposition gas mixture including a nitride source compound in the processing chamber to form no more than one monolayer of metal nitride, supplying a second purge gas mixture into the processing chamber to remove excess nitride source compound and reaction byproducts from the processing chamber, and exposing the substrate to plasma using a microwave plasma source.Type: GrantFiled: May 11, 2020Date of Patent: May 9, 2023Assignee: Applied Materials, Inc.Inventors: Wenyi Liu, Wei Tang, Srinivas Gandikota, Yixiong Yang, Yong Wu, Jianqiu Guo, Arkaprava Dan, Mandyam Sriram
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Patent number: 11621160Abstract: A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.Type: GrantFiled: August 2, 2021Date of Patent: April 4, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Eswaranand Venkatasubramanian, Srinivas Gandikota, Kelvin Chan, Atashi Basu, Abhijit Basu Mallick
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Patent number: 11621226Abstract: A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.Type: GrantFiled: February 9, 2021Date of Patent: April 4, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Yong Wu, Srinivas Gandikota, Abhijit Basu Mallick, Srinivas D. Nemani
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Publication number: 20230097400Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 ? to less than or equal to 50 ?. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-? metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Applicant: Applied Materials, Inc.Inventors: Srinivas Gandikota, Steven C.H. Hung, Mandyam Sriram, Jacqueline S. Wrench, Yixiong Yang, Yong Yang
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Patent number: 11587936Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.Type: GrantFiled: June 1, 2021Date of Patent: February 21, 2023Assignee: Applied Materials, Inc.Inventors: Yixiong Yang, Jacqueline S. Wrench, Yong Yang, Srinivas Gandikota, Annamalai Lakshmanan, Joung Joo Lee, Feihu Wang, Seshadri Ganguli
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Patent number: 11587764Abstract: Embodiments described herein relate to magnetic and electromagnetic systems and a method for controlling the density profile of plasma generated in a process volume of a PECVD chamber to affect deposition profile of a film. In one embodiment, a plurality of retaining brackets is disposed in a rotational magnetic housing of the magnetic housing systems. Each retaining bracket of the plurality of retaining brackets is disposed in the rotational magnetic housing with a distance d between each retaining bracket. The plurality of retaining brackets has a plurality of magnets removably disposed therein. The plurality of magnets is configured to travel in a circular path when the rotational magnetic housing is rotated around the round central opening.Type: GrantFiled: November 1, 2019Date of Patent: February 21, 2023Assignee: Applied Materials, Inc.Inventors: Srinivas Gandikota, Tza-Jing Gung, Samuel E. Gottheim, Timothy Joseph Franklin, Pramit Manna, Eswaranand Venkatasubramanian, Edward Haywood, Stephen C. Garner, Adam Fischbach
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Publication number: 20230015781Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.Type: ApplicationFiled: July 15, 2021Publication date: January 19, 2023Applicant: Applied Materials, Inc.Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang