Patents by Inventor Srinivas Venkataraman
Srinivas Venkataraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230245964Abstract: A mixed pitch method of placing pads in a ball grid array (BGA) package having a BGA substrate and a plurality of connectors arranged in an array and connected via the pads to the BGA substrate. Selected pairs of the pads are placed on the BGA substrate at a distance defined by a first pitch P1. Ground pads are placed on the BGA substrate at a distance from the selected pairs of pads defined by a second pitch P2, wherein P2=M*P1 and M is greater than one. The selected pairs of the pads on the BGA substrate are also placed at a distance from other selected pairs of the pads defined by the second pitch P2.Type: ApplicationFiled: April 7, 2023Publication date: August 3, 2023Inventors: Granthana Kattehalli Rangaswamy, Arvind Hanumantharayappa, Srinivas Venkataraman
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Patent number: 11652035Abstract: A mixed pitch method of placing pads in a ball grid array (BGA) package having a BGA substrate and a plurality of connectors arranged in an array and connected via the pads to the BGA substrate. Selected pairs of the pads are placed on the BGA substrate at a distance defined by a first pitch P1. Ground pads are placed on the BGA substrate at a distance from the selected pairs of pads defined by a second pitch P2, wherein P2=M*P1 and M is greater than one. The selected pairs of the pads on the BGA substrate are also placed at a distance from other selected pairs of the pads defined by the second pitch P2.Type: GrantFiled: November 4, 2020Date of Patent: May 16, 2023Assignee: Juniper Networks, Inc.Inventors: Granthana Kattehalli Rangaswamy, Arvind Hanumantharayappa, Srinivas Venkataraman
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Publication number: 20210057319Abstract: A mixed pitch method of placing pads in a ball grid array (BGA) package having a BGA substrate and a plurality of connectors arranged in an array and connected via the pads to the BGA substrate. Selected pairs of the pads are placed on the BGA substrate at a distance defined by a first pitch P1. Ground pads are placed on the BGA substrate at a distance from the selected pairs of pads defined by a second pitch P2, wherein P2=M*P1 and M is greater than one. The selected pairs of the pads on the BGA substrate are also placed at a distance from other selected pairs of the pads defined by the second pitch P2.Type: ApplicationFiled: November 4, 2020Publication date: February 25, 2021Inventors: Granthana Kattehalli Rangaswamy, Arvind Hanumantharayappa, Srinivas Venkataraman
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Patent number: 10840173Abstract: A mixed pitch method of placing pads in a ball grid array (BGA) package having a. BGA substrate and a plurality of connectors arranged in an array and connected via the pads to the BGA substrate. Selected pairs of the pads are placed on the BGA substrate at a distance defined by a first pitch PT. Ground pads are placed on the BGA substrate at a distance from the selected pairs of pads defined by a second pitch P2, wherein P2=M*P1 and M is greater than one. The selected pairs of the pads on the BGA substrate are also placed at a distance from other selected pairs of the pads defined by the second pitch P2.Type: GrantFiled: September 28, 2018Date of Patent: November 17, 2020Assignee: Juniper Networks, Inc.Inventors: Granthana Kattehalli Rangaswamy, Arvind Hanumantharayappa, Srinivas Venkataraman
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Publication number: 20200105650Abstract: A mixed pitch method of placing pads in a ball grid array (BGA) package having a. BGA substrate and a plurality of connectors arranged in an array and connected via the pads to the BGA substrate. Selected pairs of the pads are placed on the BGA substrate at a distance defined by a first pitch PT. Ground pads are placed on the BGA substrate at a distance from the selected pairs of pads defined by a second pitch P2, K wherein P2=M*P1 and M is greater than one. The selected pairs of the pads on the BGA substrate are also placed at a distance from other selected pairs of the pads defined by the second pitch P2.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Granthana Kattehalli Rangaswamy, Arvind Hanumantharayappa, Srinivas Venkataraman
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Patent number: 8813015Abstract: A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.Type: GrantFiled: December 21, 2012Date of Patent: August 19, 2014Assignee: Juniper Networks, Inc.Inventors: Srinivas Vaduvatha, Srinivas Venkataraman, Anurag P. Gupta, Praveen Garapally, Norman Bristol, Dibyendu Sen
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Patent number: 8427892Abstract: A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.Type: GrantFiled: June 8, 2011Date of Patent: April 23, 2013Assignee: Juniper Networks, Inc.Inventors: Srinivas Venkataraman, Praveen Garapally
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Patent number: 8341584Abstract: A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.Type: GrantFiled: December 31, 2010Date of Patent: December 25, 2012Assignee: Juniper Networks, Inc.Inventors: Srinivas Vaduvatha, Srinivas Venkataraman, Anurag P. Gupta, Praveen Garapally, Norman Bristol, Dibyendu Sen
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Patent number: 8273994Abstract: A printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, where the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, where the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and where a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.Type: GrantFiled: December 28, 2009Date of Patent: September 25, 2012Assignee: Juniper Networks, Inc.Inventors: Boris Reynov, Ping Yue, Shreeram Siddhaye, John Cleveland, Chebrolu Srinivas, Srinivas Venkataraman
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Patent number: 8081527Abstract: A memory controller may implement variable delay elements, on a per-bit basis, in both the read and write paths. The memory controller may include multiple adjustable delay circuits associated with data lines and a strobe line, each of the adjustable delay circuits inserting an adjustable amount of delay into a signal destined to or received from one of the data lines or the strobe line. The memory controller may additionally include control logic to determine the delay amount for each of the adjustable delay circuits, the delay amount being determined to reduce static skew between each of the data lines and the strobe line.Type: GrantFiled: May 8, 2009Date of Patent: December 20, 2011Assignee: Juniper Networks, Inc.Inventors: Srinivas Venkataraman, Praveen Garapally
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Publication number: 20110235446Abstract: A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.Type: ApplicationFiled: June 8, 2011Publication date: September 29, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Srinivas VENKATARAMAN, Praveen GARAPALLY
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Patent number: 8023342Abstract: A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.Type: GrantFiled: February 10, 2011Date of Patent: September 20, 2011Assignee: Juniper Networks, Inc.Inventors: Srinivas Venkataraman, Praveen Garapally
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Patent number: 7990781Abstract: A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.Type: GrantFiled: June 23, 2009Date of Patent: August 2, 2011Assignee: Juniper Networks, Inc.Inventors: Srinivas Venkataraman, Praveen Garapally
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Publication number: 20110155434Abstract: A printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, where the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, where the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and where a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.Type: ApplicationFiled: December 28, 2009Publication date: June 30, 2011Applicant: Juniper Networks Inc.Inventors: Boris REYNOV, Ping Yue, Shreeram Siddhaye, John Cleveland, Chebrolu Srinivas, Srinivas Venkataraman
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Publication number: 20110128793Abstract: A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.Type: ApplicationFiled: February 10, 2011Publication date: June 2, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Srinivas VENKATARAMAN, Praveen GARAPALLY
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Patent number: 7911857Abstract: A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.Type: GrantFiled: June 10, 2009Date of Patent: March 22, 2011Assignee: Juniper Networks, Inc.Inventors: Srinivas Venkataraman, Praveen Garapally
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Patent number: 7113418Abstract: Memory systems and methods are described. In one embodiment, a circuit board has front and back surfaces. At least one memory device having a plurality of pins is mounted on the front surface of the circuit board. At least one other memory device having a plurality of pins is mounted on the back surface of the circuit board. The memory devices are mounted on the circuit board such that at least some pins from the one memory device align with at least some pins of the other memory device to provide aligned pin pairs. A via is disposed in the circuit board and extends between and connects individual pins of an aligned pin pair.Type: GrantFiled: November 4, 2003Date of Patent: September 26, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: William L. Oberlin, Mark R. Simpson, Srinivas Venkataraman
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Publication number: 20050097249Abstract: Memory systems and methods are described. In one embodiment, a circuit board has front and back surfaces. At least one memory device having a plurality of pins is mounted on the front surface of the circuit board. At least one other memory device having a plurality of pins is mounted on the back surface of the circuit board. The memory devices are mounted on the circuit board such that at least some pins from the one memory device align with at least some pins of the other memory device to provide aligned pin pairs. A via is disposed in the circuit board and extends between and connects individual pins of an aligned pin pair.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Inventors: William Oberlin, Mark Simpson, Srinivas Venkataraman