Patents by Inventor Srinivasa Rao Muppala

Srinivasa Rao Muppala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11281513
    Abstract: Embodiments are disclosed for managing heap metadata corruption. The techniques include detecting a metadata corruption error in a first heap disposed in a first region of memory. The techniques also include generating a second heap in a free memory region that is disposed beyond a break value address of a memory allocation system. The techniques further include updating a first entry for the first heap in a heap directory. Additionally, the techniques include generating a second entry for the second heap in the heap directory. The techniques also include processing a call to the memory allocation system for the first heap based on the first entry and the second entry.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sreenivas Makineedi, Srinivasa Rao Muppala, Rama Mothey Tenjarla, Vidya Makineedi, Douglas Griffith
  • Patent number: 11263114
    Abstract: Threads of a multithreaded application may be scheduled to different cores and executed in various orders and at various frequencies. Controlling how the threads are scheduled and clock rates of processor cores enables testing multiple possible execution scenarios, which may force previously unknown timing window problems to occur. These timing window problems may then be detected.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sreenivas Makineedi, Douglas Griffith, Emmanuelle Samir Hanna Matta, Evelyn Tingmay Yeung, Srinivasa Rao Muppala
  • Patent number: 10996990
    Abstract: Embodiments include method, systems and computer program products for performing Spectre mitigation on a workload. The method includes starting, by at least one processor of a plurality of processors, a process. The at least one processor determines that the process is a kernel process. The at least one processor determines that an interrupt has occurred in response to the determination that the process is a kernel process. The at least one processor processes the interrupt in response to determining that an interrupt has occurred. The at least one processor suppresses a malware mitigation to be applied to the kernel process in response to interrupt being processed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sreenivas Makineedi, Douglas Griffith, Srinivasa Rao Muppala, Anil Kalavakolanu, Shanna Beck
  • Publication number: 20210089428
    Abstract: Threads of a multithreaded application may be scheduled to different cores and executed in various orders and at various frequencies. Controlling how the threads are scheduled and clock rates of processor cores enables testing multiple possible execution scenarios, which may force previously unknown timing window problems to occur. These timing window problems may then be detected.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Sreenivas Makineedi, Douglas Griffith, Emmanuelle Samir Hanna Matta, Evelyn Tingmay Yeung, Srinivasa Rao Muppala
  • Publication number: 20200387416
    Abstract: Embodiments are disclosed for managing heap metadata corruption. The techniques include detecting a metadata corruption error in a first heap disposed in a first region of memory. The techniques also include generating a second heap in a free memory region that is disposed beyond a break value address of a memory allocation system. The techniques further include updating a first entry for the first heap in a heap directory. Additionally, the techniques include generating a second entry for the second heap in the heap directory. The techniques also include processing a call to the memory allocation system for the first heap based on the first entry and the second entry.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Sreenivas MAKINEEDI, Srinivasa Rao Muppala, Rama Mothey Tenjarla, Vidya MAKINEEDI, Douglas GRIFFITH
  • Patent number: 10838635
    Abstract: Examples of techniques for deferred disclaim of memory pages are described herein. An aspect includes, based on freeing of a last allocation on a first memory page, placing, by a processor, the first memory page on a deferred disclaim list. Another aspect includes, based on freeing of the last allocation on the first memory page, setting, by the processor, a first hidden flag in a first page table entry corresponding to the first memory page.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas Griffith, Sreenivas Makineedi, Srinivasa Rao Muppala, Evan Zoss, Mathew Accapadi, Anil Kalavakolanu
  • Publication number: 20200285405
    Abstract: Examples of techniques for deferred disclaim of memory pages are described herein. An aspect includes, based on freeing of a last allocation on a first memory page, placing, by a processor, the first memory page on a deferred disclaim list.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: DOUGLAS GRIFFITH, SREENIVAS MAKINEEDI, Srinivasa Rao Muppala, Evan Zoss, Mathew Accapadi, Anil Kalavakolanu
  • Publication number: 20200159580
    Abstract: Embodiments include method, systems and computer program products for performing Spectre mitigation on a workload. The method includes starting, by at least one processor of a plurality of processors, a process. The at least one processor determines that the process is a kernel process. The at least one processor determines that an interrupt has occurred in response to the determination that the process is a kernel process. The at least one processor processes the interrupt in response to determining that an interrupt has occurred. The at least one processor suppresses a malware mitigation to be applied to the kernel process in response to interrupt being processed.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Inventors: Sreenivas Makineedi, Douglas Griffith, Srinivasa Rao Muppala, Anil Kalavakolanu, Shanna Beck
  • Publication number: 20200065013
    Abstract: A system includes a memory system and a processing system operably coupled to the memory system. The memory system includes a kernel address space associated with a kernel of an operating system and a user address space associated with a plurality of processes configured to interface with the kernel. The processing system is configured to perform a plurality of operations including determining that one or more new memory pages are assigned to the kernel address space. A kernel submodule of the kernel associated with the one or more new memory pages is identified. Clearing of the one or more new memory pages is skipped based on a memory initialization configuration associated with the kernel submodule. Access to the one or more new memory pages is provided.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Douglas Griffith, Reginald D. Harvey, Sreenivas Makineedi, Srinivasa Rao Muppala, Paul Vaters