Patents by Inventor Srinivasa Rao Sabbineni
Srinivasa Rao Sabbineni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230288949Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for regulators providing shared current from multiple input supplies. A regulator can include a first portion configured to receive a first supply voltage and to output a first current drawn from the first supply voltage by a load, and a second portion configured to receive a second supply voltage. The regulator can include a current control circuit configured to, responsive to a load current corresponding the load meeting a particular criteria, initiate current sharing such that the load current is subsequently shared between the first supply voltage and the second supply voltage.Type: ApplicationFiled: July 28, 2022Publication date: September 14, 2023Inventors: Ekram H. Bhuiyan, Jayaprakash Naradasi, Srinivasa Rao Sabbineni, Michael Mostovoy
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Publication number: 20180173619Abstract: In a storage device having a storage controller and multiple memory channels, each memory channel has a memory channel controller. The storage controller, in response to a host command to perform a respective read operation at a logical address specified by the host command, identifies the memory channel based on the specified logical address, and also identifies a portion of logical to physical address mapping information corresponding to the logical address. The storage controller sends to a controller of the identified memory channel a read command that includes information identifying the portion of logical to physical address mapping information corresponding to the logical address. Using that information, the memory channel controller translates the logical address into a physical address and reads data from the physical address.Type: ApplicationFiled: April 19, 2017Publication date: June 21, 2018Inventors: Vijay Sivasankaran, Srinivasa Rao Sabbineni, Saugata Das, Indraneel Mukherjee, Nitin Gupta
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Patent number: 10001797Abstract: Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.Type: GrantFiled: July 25, 2016Date of Patent: June 19, 2018Assignee: SanDisk Technologies LLCInventors: Srinivasa Rao Sabbineni, Bhavin Odedara, Jayanth Mysore Thimmaiah
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Publication number: 20180024581Abstract: Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.Type: ApplicationFiled: July 25, 2016Publication date: January 25, 2018Applicant: SanDisk Technologies LLCInventors: Srinivasa Rao Sabbineni, Bhavin Odedara, Jayanth Mysore Thimmaiah
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Publication number: 20180026646Abstract: A phase-locked loop (PLL) circuit may be configured to generate a plurality of oscillating signals based on a single control voltage generated based on a phase difference between an input signal and a feedback signal. One of the plurality of oscillating signals may be used to generate the feedback signal.Type: ApplicationFiled: July 25, 2016Publication date: January 25, 2018Applicant: SanDisk Technologies LLCInventors: Bhavin Odedara, Srikanth Bojja, Jayanth Mysore Thimmaiah, Srinivasa Rao Sabbineni
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Patent number: 9747958Abstract: An electronic device may receive a supply voltage from another external device, and detect when a level of the supply voltage drops below a threshold. In response, a controller of the electronic device may deactivate an interface configured for communication with the other electronic device. The controller may manage time periods and time period counters to determine when the check whether to reactivate the interface or conclude that the other external device is non-compliant.Type: GrantFiled: October 30, 2015Date of Patent: August 29, 2017Assignee: SanDisk Technologies LLCInventors: Srinivasa Rao Sabbineni, Jayanth Mysore Thimmaiah, Anand Venkitachalam, Bhavin Odedara
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Publication number: 20170125068Abstract: An electronic device may receive a supply voltage from another external device, and detect when a level of the supply voltage drops below a threshold. In response, a controller of the electronic device may deactivate an interface configured for communication with the other electronic device. The controller may manage time periods and time period counters to determine when the check whether to reactivate the interface or conclude that the other external device is non-compliant.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Inventors: Srinivasa Rao Sabbineni, Jayanth Mysore Thimmaiah, Anand Venkitachalam, Bhavin Odedara
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Patent number: 9524799Abstract: Methods and apparatuses for performing receive and transmit path tuning of a toggle mode interface between a primary controller and a secondary controller is disclosed. A first component having a variable setting and connected with a data bus of the interface is iteratively adjusted. For each setting of the first component, test data written to the secondary controller and a delay unit having a variable delay setting and connected with a strobe line of the interface is adjusted. Delay settings are identified where the read data is equal to the written data. Settings for the first component and corresponding delay setting that produce the largest range of delay settings where the read data is equal to the written data is selected. The first component may correspond to a driver unit in the primary controller or an ODT unit in the secondary controller.Type: GrantFiled: June 15, 2015Date of Patent: December 20, 2016Assignee: SanDisk Technologies LLCInventors: Sateesh Desireddi, Srinivasa Rao Sabbineni, Shiv Harit Mathur
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Publication number: 20160189758Abstract: Methods and apparatuses for performing receive and transmit path tuning of a toggle mode interface between a primary controller and a secondary controller is disclosed. A first component having a variable setting and connected with a data bus of the interface is iteratively adjusted. For each setting of the first component, test data written to the secondary controller and a delay unit having a variable delay setting and connected with a strobe line of the interface is adjusted. Delay settings are identified where the read data is equal to the written data. Settings for the first component and corresponding delay setting that produce the largest range of delay settings where the read data is equal to the written data is selected. The first component may correspond to a driver unit in the primary controller or an ODT unit in the secondary controller.Type: ApplicationFiled: June 15, 2015Publication date: June 30, 2016Applicant: SanDisk Technologies Inc.Inventors: Sateesh Desireddi, Srinivasa Rao Sabbineni, Shiv Harit Mathur
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Patent number: 8669817Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: GrantFiled: November 21, 2011Date of Patent: March 11, 2014Assignee: SanDisk Technologies Inc.Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi
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Publication number: 20120062326Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi
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Patent number: 8085099Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: GrantFiled: April 6, 2010Date of Patent: December 27, 2011Assignee: SanDisk Technologies Inc.Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi
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Publication number: 20110241784Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: ApplicationFiled: April 6, 2010Publication date: October 6, 2011Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi