Patents by Inventor Srinivasan RAGHAVAN
Srinivasan RAGHAVAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973137Abstract: The present subject matter provides a High Mobility Electron Transistor (HEMT) comprising: a substrate, a nucleation layer provided on the substrate, a channel layer, and a buffer layer formed between the nucleation layer and the channel layer. The buffer layer comprises a vertical stack of p-n junctions. Each p-n junction of the vertical stack of p-n junctions comprises an n-type layer provided on a p-type layer. The n-type layer and the p-type layer are parallel to the substrate.Type: GrantFiled: December 5, 2019Date of Patent: April 30, 2024Assignee: Indian Institute of ScienceInventors: Srinivasan Raghavan, Navakanta Bhat, Rohith Soman
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Patent number: 11522078Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.Type: GrantFiled: July 6, 2018Date of Patent: December 6, 2022Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Rohith Soman, Ankit Soni, Mayank Shrivastava, Srinivasan Raghavan, Navakant Bhat
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Patent number: 11368307Abstract: In general, techniques are described for using zero-knowledge proofs and digital signatures to verify the authenticity of log records generated by multiple parties, at least in some cases without exposing personally identifiable information for the parties.Type: GrantFiled: November 26, 2019Date of Patent: June 21, 2022Assignee: Equinix, Inc.Inventors: Anand Ozarkar, Srinivasan Raghavan, Imam Sheikh, Ankur Sharma
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Publication number: 20220020871Abstract: The present subject matter provides a High Mobility Electron Transistor (HEMT) comprising: a substrate, a nucleation layer provided on the substrate, a channel layer, and a buffer layer formed between the nucleation layer and the channel layer. The buffer layer comprises a vertical stack of p-n junctions. Each p-n junction of the vertical stack of p-n junctions comprises an n-type layer provided on a p-type layer. The n-type layer and the p-type layer are parallel to the substrate.Type: ApplicationFiled: December 5, 2019Publication date: January 20, 2022Inventors: Srinivasan RAGHAVAN, Navakanta BHAT, Rohith SOMAN
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Patent number: 11218313Abstract: A trusted device is positioned within a private consensus network. The trusted device includes a memory and processing circuitry in communication with the memory. The processing circuitry is configured to obtain, from a private distributed ledger associated with the private consensus network, rules associated with the private consensus network, the private distributed ledger being accessible only to devices positioned within the private consensus network, to identify one or more other trusted devices positioned within the private consensus network, to receive, from an unidentified device positioned within the private consensus network, an identity verification request to identify the unidentified device within the private consensus network, to determine, based on the obtained rules, whether to approve or deny the identity verification request, and to communicate, to the one or more other trusted devices, a vote indicative of the determination of whether to approve or deny the identity verification request.Type: GrantFiled: December 5, 2019Date of Patent: January 4, 2022Assignee: Equinix, Inc.Inventors: Srinivasan Raghavan, Sreekanth Narayanan, Neeraj Kumar Kukreti
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Patent number: 10854719Abstract: The present invention provides a metal nitride platform for semiconductor devices, including, a pre-defined array of catalyst sites, disposed on a substrate. Metal nitride islands with lateral to vertical size ratios of at least greater than one (1) are disposed on the array of catalyst sites, where the surfaces of the metal nitride islands are with reduced dislocation densities and side walls with bending of dislocations. The platform of metal nitride islands is further used to build electrically and optically-active devices. The present invention also provides a process for the preparation of a metal nitride platform, selectively, on the array of catalyst sites, in the presence of a reactive gas and precursors and under preferred reaction conditions, to grow metal nitride islands with lateral to vertical size ratios of at least greater than one (1).Type: GrantFiled: March 17, 2017Date of Patent: December 1, 2020Assignee: Indian Institute of ScienceInventors: Srinivasan Raghavan, Hareesh Chandrasekar, Nagaboopathy Mohan, Dhayalan Shakthivel
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Patent number: 10840348Abstract: The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 ?mm, interface trap density <1010 mm?2eV?1 and gate leakage below 200 nA/mm at the OFF-state breakdown.Type: GrantFiled: August 28, 2018Date of Patent: November 17, 2020Assignee: Indian Institute of ScienceInventors: Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan, Navakanta Bhat
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Publication number: 20200227543Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.Type: ApplicationFiled: July 6, 2018Publication date: July 16, 2020Inventors: Rohith SOMAN, Ankit SONI, Mayank SHRIVASTAVA, Srinivasan RAGHAVAN, Navakant BHAT
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Publication number: 20190067440Abstract: The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 ?mm, interface trap density <1010 mm?2eV?1 and gate leakage below 200 nA/mm at the OFF-state breakdown.Type: ApplicationFiled: August 28, 2018Publication date: February 28, 2019Inventors: Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan, Navakanta Bhat
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Publication number: 20170278932Abstract: The present invention provides a metal nitride platform for semiconductor devices, including, a pre-defined array of catalyst sites, disposed on a substrate. Metal nitride islands with lateral to vertical size ratios of at least greater than one (1) are disposed on the array of catalyst sites, where the surfaces of the metal nitride islands are with reduced dislocation densities and side walls with bending of dislocations. The platform of metal nitride islands is further used to build electrically and optically-active devices. The present invention also provides a process for the preparation of a metal nitride platform, selectively, on the array of catalyst sites, in the presence of a reactive gas and precursors and under preferred reaction conditions, to grow metal nitride islands with lateral to vertical size ratios of at least greater than one (1).Type: ApplicationFiled: March 17, 2017Publication date: September 28, 2017Inventors: Srinivasan RAGHAVAN, Hareesh CHANDRASEKAR, Nagaboopathy MOHAN, Dhayalan SHAKTHIVEL
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Patent number: 9068275Abstract: A grain starter for use in solidification of molten metallic material forming an article having a directional grain structure and a method for solidifying an article having a directional grain structure with a substantial absence of stray grains. The grain starter comprises a grain-starting material that initiates grain growth in the molten metallic material in a preselected crystallographic direction. The grain-starting material has a melting temperature higher than the metallic material forming the article lest the grain starter be modified by contact with the molten material. The grain starter further includes a feature that modifies heat transfer characteristics of the metallic material in contact with it in order to produce an article having grains oriented in the preselected crystallographic orientation and modifies the profile of the advancing solidification front. The article is substantially free of stray grains not oriented in the preselected crystallographic direction.Type: GrantFiled: May 8, 2013Date of Patent: June 30, 2015Assignee: General Electric CompanyInventors: Shan Liu, Warren Tan King, Srinivasan Raghavan, Arthur S. Peck, Dayananda Narayana
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Publication number: 20140332175Abstract: A grain starter for use in solidification of molten metallic material forming an article having a directional grain structure and a method for solidifying an article having a directional grain structure with a substantial absence of stray grains. The grain starter comprises a grain-starting material that initiates grain growth in the molten metallic material in a preselected crystallographic direction. The grain-starting material has a melting temperature higher than the metallic material forming the article lest the grain starter be modified by contact with the molten material. The grain starter further includes a feature that modifies heat transfer characteristics of the metallic material in contact with it in order to produce an article having grains oriented in the preselected crystallographic orientation and modifies the profile of the advancing solidification front. The article is substantially free of stray grains not oriented in the preselected crystallographic direction.Type: ApplicationFiled: May 8, 2013Publication date: November 13, 2014Applicant: GENERAL ELECTRIC COMPANYInventors: Shan LIU, Warren Tan KING, Srinivasan RAGHAVAN, Arthur S. PECK, Dayananda NARAYANA
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Patent number: 8505173Abstract: A socket device (10) for securing an end of a load bearing member (22) includes first socket members (26a and 26b) and second socket members (28a and 28b) that are distinct, separate pieces of material. The second socket members (28a and 28b) are spaced apart from each other at a desired angle and rigidly secured on one side to one of the first socket members (26a) and on another side to the other first socket member (26b) to form the socket (24). A disclosed example includes cooperating tabs (38) and recesses or openings (34) for securing the socket members together in a rigidly fixed alignment.Type: GrantFiled: August 29, 2006Date of Patent: August 13, 2013Assignee: Otis Elevator CompanyInventors: John T. Pitts, Boris G. Traktovenko, Kotur Srinivasan Raghavan, Vijal Mohan Veeramalla, Laxmipathi Chilaveni, Kandi Puroshotham Pavan Kumar, Shailendra Singh, Saravana Kumar Kandasami
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Publication number: 20090307876Abstract: A socket device (10) for securing an end of a load bearing member (22) includes first socket members (26a and 26b) and second socket members (28a and 28b) that are distinct, separate pieces of material. The second socket members (28a and 28b) are spaced apart from each other at a desired angle and rigidly secured on one side to one of the first socket members (26a) and on another side to the other first socket member (26b) to form the socket (24). A disclosed example includes cooperating tabs (38) and recesses or openings (34) for securing the socket members together in a rigidly fixed alignment.Type: ApplicationFiled: August 29, 2006Publication date: December 17, 2009Inventors: John T. Pitts, Boris G. Traktovenko, Kotur Srinivasan Raghavan, Vijai Mohan Veeramalla, Laxmipathi Chilaveni, Kandi Purushotham Pavan Kumar, Shailendra Singh, Saravana Kumar Kandasami