Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.

Abstract: An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.

Abstract: An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion.

Abstract: An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion.

Abstract: A data processing device includes a first memory for use during normal operation of the device and a second memory for use during testing. The second memory stores a set of test patterns for testing of a functional module. When the data processing device is in a normal (i.e. non-test) mode of operation, data is retrieved from a first memory based on a received memory address. The retrieved data is applied to the functional module of the data processing device to perform a designated function. When the data processing device is in a test mode of operation, received memory addresses are provided to the second memory for retrieval of a test pattern associated with the address. The test pattern is applied to the functional module to generate an output pattern. The result of a test is determined by comparing the output pattern to an expected pattern.

Abstract: A data processing device includes a first memory for use during normal operation of the device and a second memory for use during testing. The second memory stores a set of test patterns for testing of a functional module. When the data processing device is in a normal (i.e. non-test) mode of operation, data is retrieved from a first memory based on a received memory address. The retrieved data is applied to the functional module of the data processing device to perform a designated function. When the data processing device is in a test mode of operation, received memory addresses are provided to the second memory for retrieval of a test pattern associated with the address. The test pattern is applied to the functional module to generate an output pattern. The result of a test is determined by comparing the output pattern to an expected pattern.