Abstract: An embodiment of an apparatus may include a memory package with one or more memory die on an internal input/output (IO) path of the memory package, and an interface module communicatively coupled to the one or more memory die through the internal IO path, the interface module including circuitry to perform IO external to the memory package at a first IO width and a first IO speed, and perform IO internal to the memory package at a second IO width and a second IO speed, wherein one or more of the second IO width is different from the first IO width and the second IO speed is different from the first IO speed. Other embodiments are disclosed and claimed.

Abstract: Technology to provide a multi-phase clocking scheme for a memory device includes generating, based on a first clock signal having a first frequency, multi-phase clock signals for a memory device having a second frequency, where the second frequency is a fraction of the first frequency, generating local clock signals for data channels of the memory device based on the multi-phase clock signals, where the local clock signals are synchronous with respective rising edges of the multi-phase clock signals, and providing output data for the data channels of the memory device in an output data sequence based on the local clock signals. In some embodiments, the second frequency is one-half of the first frequency, and the multi-phase clock signals are four-phase clock signals. In some embodiments, the output data is clocked out at an effective rate equal to the first frequency based on the local clock signals.

Abstract: An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to provide duty cycle correction (DCC) for one or more write paths of the NAND memory. Other examples are disclosed and claimed.

Abstract: An embodiment of a memory device may include a substrate, a first memory array of three-dimensional (3D) NAND cells disposed on the substrate, an isolation trench disposed on the substrate adjacent to the first memory array, and an input/output (IO) contact positioned within the isolation trench. Other embodiments are disclosed and claimed.

Abstract: In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.

Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a device that includes an interface for communication with a host. The device includes components that can operate during at least one of read link training and duty cycle distortion compensation operation.

Abstract: In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.

Abstract: An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.

Abstract: An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.

Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a device that includes an interface for communication with a host. The device includes components that can operate during at least one of read link training and duty cycle distortion compensation operation.

Abstract: Apparatus, methods, and systems are herein described for providing a method for calibrating a channel by employing a training sequence during at least one blanking interval. In one embodiment, an apparatus includes a first control logic to send a command to generate a predetermined data pattern during at least one blanking interval. In addition, the apparatus includes a second control logic to determine whether a received data pattern matches the predetermined data pattern.