Patents by Inventor Srivatsa Vaddagiri
Srivatsa Vaddagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200285584Abstract: Aborting a cache memory flush may include initiating a flush operation in which a plurality of cache lines are flushed from a cache memory associated with a processor core that is entering a power collapse mode. Assertion of a wake-up signal associated with the processor core entering the power collapse mode may be detected. The wake-up signal may occur before completion of the flush operation. The flush operation may cease or abort in response to detecting the wake-up signal.Type: ApplicationFiled: March 4, 2019Publication date: September 10, 2020Inventors: Raghavendra Srinivas, Kaustav Roychowdhury, Siddesh Halavarthi Math Revana, Srivatsa Vaddagiri, Satyaki Mukherjee
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Patent number: 9785481Abstract: Methods and apparatus for power-based scheduling of tasks among processors are disclosed. A method may include executing processor executable code on one or more of the processors to prompt a plurality of executable tasks for scheduling among the processors. Processor-demand information is obtained about the plurality of executable tasks in addition to capacity information for each of the processors. Processor power information for each of the processors is also obtained, and the plurality of executable tasks are scheduled on the lowest power processors where processor-demands of the tasks are satisfied.Type: GrantFiled: July 24, 2015Date of Patent: October 10, 2017Assignee: QUALCOMM Innovation Center, Inc.Inventors: Stephen Muckle, Srivatsa Vaddagiri, Syed Rameez Mustafa
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Publication number: 20170097854Abstract: An example apparatus and method are disclosed for scheduling a plurality of threads for execution on a cluster of a plurality of clusters. The method includes determining that a first thread is dependent on a second thread. The first and second threads process a workload for a common frame. The method also includes selecting a cluster of a plurality of clusters. The method further includes scheduling the first and second threads for execution on the selected cluster.Type: ApplicationFiled: July 26, 2016Publication date: April 6, 2017Inventors: Premal Shah, Omprakash Dhyade, Srivatsa Vaddagiri, Stephen Muckle
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Patent number: 9400518Abstract: Systems and methods for temporarily adjusting the frequency of processors are disclosed. A computing device may include a plurality of processors that are each configured to execute one or more tasks at a corresponding one of a plurality of frequencies. A scheduling component migrates tasks between the processors to balance a load that is processed by the plurality of processors. A governor component includes a frequency adjustment component to control a frequency of each of the processors and a frequency synchronization component that detects when the scheduling component is migrating one of the tasks from a source processor to a destination processor. The synchronization component increases, based upon a frequency of the source processor, a frequency of the destination processor.Type: GrantFiled: October 10, 2013Date of Patent: July 26, 2016Assignee: Qualcomm Innovation Center, Inc.Inventors: Varad Deshmukh, Stephen Muckle, Bryan Huntsman, Veena Sambasivan, Srivatsa Vaddagiri
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Publication number: 20160026507Abstract: Methods and apparatus for power-based scheduling of tasks among processors are disclosed. A method may include executing processor executable code on one or more of the processors to prompt a plurality of executable tasks for scheduling among the processors. Processor-demand information is obtained about the plurality of executable tasks in addition to capacity information for each of the processors. Processor power information for each of the processors is also obtained, and the plurality of executable tasks are scheduled on the lowest power processors where processor-demands of the tasks are satisfied.Type: ApplicationFiled: July 24, 2015Publication date: January 28, 2016Inventors: Stephen Muckle, Srivatsa Vaddagiri, Syed Rameez Mustafa
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Publication number: 20140365808Abstract: Systems and methods for temporarily adjusting the frequency of processors are disclosed. A computing device may include a plurality of processors that are each configured to execute one or more tasks at a corresponding one of a plurality of frequencies. A scheduling component migrates tasks between the processors to balance a load that is processed by the plurality of processors. A governor component includes a frequency adjustment component to control a frequency of each of the processors and a frequency synchronization component that detects when the scheduling component is migrating one of the tasks from a source processor to a destination processor. The synchronization component increases, based upon a frequency of the source processor, a frequency of the destination processor.Type: ApplicationFiled: October 10, 2013Publication date: December 11, 2014Applicant: Qualcomm Innovation Center, Inc.Inventors: Varad Deshmukh, Steve Muckle, Bryan Huntsman, Veena Sambasivan, Srivatsa Vaddagiri
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Patent number: 8645963Abstract: Techniques for grouping two or more threads based on lock contention information are provided. The techniques include determining lock contention information with respect to two or more threads, using the lock contention information with respect to the two or more threads to determine lock affinity between the two or more threads, using the lock affinity between the two or more threads to group the two or more threads into one or more thread clusters, and using the one or more thread clusters to perform scheduling of one or more threads.Type: GrantFiled: November 5, 2009Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Manish Gupta, Anithra P. Janakiraman, Prashanth K. Nageshappa, Srivatsa Vaddagiri
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Patent number: 8516492Abstract: A method and system are provided for load balancing and partial task-processor binding. The method may provide for migrating at least one first task partially bound to and executing on at least one first processor. In accordance with the method, if at least one first condition is true, then the at least one first task may be migrated to at least one second processor such that the at least one second processor executes the at least one first task. Moreover, in accordance with the method, if at least one second condition is true, the at least one first task may be migrated back to the at least one first processor such that the at least one first processor executes the at least one first task.Type: GrantFiled: June 11, 2010Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventor: Srivatsa Vaddagiri
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Publication number: 20110307903Abstract: A method and system are provided for load balancing and partial task-processor binding. The method may provide for migrating at least one first task partially bound to and executing on at least one first processor. In accordance with the method, if at least one first condition is true, then the at least one first task may be migrated to at least one second processor such that the at least one second processor executes the at least one first task. Moreover, in accordance with the method, if at least one second condition is true, the at least one first task may be migrated back to the at least one first processor such that the at least one first processor executes the at least one first task.Type: ApplicationFiled: June 11, 2010Publication date: December 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Srivatsa Vaddagiri
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Publication number: 20110107340Abstract: Techniques for grouping two or more threads based on lock contention information are provided. The techniques include determining lock contention information with respect to two or more threads, using the lock contention information with respect to the two or more threads to determine lock affinity between the two or more threads, using the lock affinity between the two or more threads to group the two or more threads into one or more thread clusters, and using the one or more thread clusters to perform scheduling of one or more threads.Type: ApplicationFiled: November 5, 2009Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manish Gupta, Anithra P. Janakiraman, Prashanth K. Nageshappa, Srivatsa Vaddagiri
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Patent number: 7739685Abstract: A method and system for decoupling a central processing unit (CPU) of a plurality of hot CPUs from its assigned tasks. The hot CPUs are managed by an operating system of a computer system. A special flag is set, denoting that the CPU is to be decoupled from its assigned tasks. A special task coupled to the CPU is given a suitable scheduling policy and priority, wherein the special task gets enough continuous execution time to finish its job before another task executes on the CPU. The special task examines the special flag and decouples the first CPU from its assigned tasks after determining that the special flag has been set, wherein the special task does not relinquish control of the CPU. The decoupling of tasks from the CPU leaves at least one remaining CPU and occurs while the at least one remaining CPU is hot.Type: GrantFiled: January 6, 2005Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventor: Srivatsa Vaddagiri
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Publication number: 20060150187Abstract: A method and system for decoupling a central processing unit (CPU) of a plurality of hot CPUs from its assigned tasks. The hot CPUs are managed by an operating system of a computer system. A special flag is set, denoting that the CPU is to be decoupled from its assigned tasks. A special task coupled to the CPU is given a suitable scheduling policy and priority, wherein the special task gets enough continuous execution time to finish its job before another task executes on the CPU. The special task examines the special flag and decouples the first CPU from its assigned tasks after determining that the special flag has been set, wherein the special task does not relinquish control of the CPU. The decoupling of tasks from the CPU leaves at least one remaining CPU and occurs while the at least one remaining CPU is hot.Type: ApplicationFiled: January 6, 2005Publication date: July 6, 2006Applicant: International Business Machines CorporationInventor: Srivatsa Vaddagiri
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Patent number: 6988264Abstract: Debugging multiple tasks, using a single instance of a debugger application intended to be only capable of debugging a single task, is performed by intercepting system calls made by the debugger application to the operating system. The intercepted system calls are directed to an appropriate task, which is one amongst the multiple tasks to be debugged.Type: GrantFiled: March 18, 2002Date of Patent: January 17, 2006Assignee: International Business Machines CorporationInventors: Dipankar Sarma, Srivatsa Vaddagiri
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Publication number: 20030177476Abstract: Debugging multiple tasks, using a single instance of a debugger application intended to be only capable of debugging a single task, is performed by intercepting system calls made by the debugger application to the operating system. The intercepted system calls are directed to an appropriate task, which is one amongst the multiple tasks to be debugged.Type: ApplicationFiled: March 18, 2002Publication date: September 18, 2003Inventors: Dipankar Sarma, Srivatsa Vaddagiri