Patents by Inventor Srivatsan Venkatesan
Srivatsan Venkatesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984161Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.Type: GrantFiled: May 25, 2022Date of Patent: May 14, 2024Assignee: Micron Technology, Inc.Inventors: Srivatsan Venkatesan, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Patent number: 11862215Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.Type: GrantFiled: August 27, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Sateesh Talasila, Chandrasekhar Mandalapu, Robert Douglas Cassel, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Srivatsan Venkatesan
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Patent number: 11715520Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells.Type: GrantFiled: April 5, 2021Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Robert Douglas Cassel, Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango
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Publication number: 20230171968Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.Type: ApplicationFiled: November 29, 2021Publication date: June 1, 2023Inventors: Srivatsan Venkatesan, Fabio Pellizzer
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Publication number: 20230069190Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Sateesh Talasila, Chandrasekhar Mandalapu, Robert Douglas Cassel, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Srivatsan Venkatesan
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Publication number: 20230018390Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: ApplicationFiled: September 13, 2022Publication date: January 19, 2023Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Patent number: 11514985Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: GrantFiled: April 5, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20220319592Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: ApplicationFiled: April 5, 2021Publication date: October 6, 2022Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20220319594Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.Type: ApplicationFiled: May 25, 2022Publication date: October 6, 2022Inventors: Srivatsan Venkatesan, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20220319595Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells.Type: ApplicationFiled: April 5, 2021Publication date: October 6, 2022Inventors: Robert Douglas Cassel, Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango
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Publication number: 20220254999Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features.Type: ApplicationFiled: February 28, 2022Publication date: August 11, 2022Inventors: Srivatsan VENKATESAN, Davide MANTEGAZZA, John GORMAN, Iniyan Soundappa ELANGO, Davide FUGAZZA, Andrea REDAELLI, Fabio PELLIZZER
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Patent number: 11348640Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.Type: GrantFiled: April 5, 2021Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventors: Srivatsan Venkatesan, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Patent number: 11348149Abstract: A computer program, computer-implemented process, and/or an apparatus may detect an event in a webpage or an application, and adjust a lead score by comparing the event with implicit lead scoring rules, explicit lead scoring rules, lead state, or any combination thereof. Using the lead score, the event is assigned to a category or classification for purposes of identifying a positive or negative lead.Type: GrantFiled: August 28, 2017Date of Patent: May 31, 2022Inventors: Srivatsan Venkatesan, Tarkeshwar Thakur, Vijayaragavan Venkatarathinam, Bhagirath Goud, Pratheeswaran Ramasamy
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Patent number: 11264567Abstract: Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.Type: GrantFiled: November 19, 2019Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Srivatsan Venkatesan, Davide Mantegazza, John Gorman, Iniyan Soundappa Elango, Davide Fugazza, Andrea Redaelli, Fabio Pellizzer
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Publication number: 20210151672Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features.Type: ApplicationFiled: November 19, 2019Publication date: May 20, 2021Applicant: INTEL CORPORATIONInventors: SRIVATSAN VENKATESAN, DAVIDE MANTEGAZZA, JOHN GORMAN, INIYAN SOUNDAPPA ELANGO, DAVIDE FUGAZZA, ANDREA REDAELLI, FABIO PELLIZZER
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Patent number: 10218654Abstract: In an approach to save-to location selection, a computing device accesses a metadata file comprising a data table. The computing device checks the data table for entries that match one or more features of a file to be saved, wherein each match is associated with a save-to location. The computing device computes confidence scores for each save-to location based on a predefined weight associated with to each feature. The computing device produces a list of recommended save-to locations based on the confidence scores. The computing device receives a user selection based on or overriding the recommendations. The computing device updates the data table with information concerning each of the features of the file and the user selection.Type: GrantFiled: September 29, 2015Date of Patent: February 26, 2019Assignee: International Business Machines CorporationInventors: Anjil R. Chinnapatlolla, Vijai Kalathur, Rajaram B. Krishnamurthy, Ajay Sood, Srivatsan Venkatesan
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Patent number: 10110529Abstract: In an approach to save-to location selection, a computing device accesses a metadata file comprising a data table. The computing device successively checks the data table for entries that match a series of features of a file to be saved. If the computing device finds one or more matches, the computing device determines an associated save-to location. If the computing device does not find a match and has exhausted all of the series of features, the computing devices determines a default save-to location. The computing device receives a user selection based on or overriding the determination. The computing device updates the data table with information concerning each of the features of the file and information concerning the user selection.Type: GrantFiled: September 29, 2015Date of Patent: October 23, 2018Assignee: International Business MachinesInventors: Anjil R. Chinnapatlolla, Vijai Kalathur, Rajaram B. Krishnamurthy, Ajay Sood, Srivatsan Venkatesan
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Publication number: 20180060929Abstract: A computer program, computer-implemented process, and/or an apparatus may detect an event in a webpage or an application, and adjust a lead score by comparing the event with implicit lead scoring rules, explicit lead scoring rules, lead state, or any combination thereof. Using the lead score, the event is assigned to a category or classification for purposes of identifying a positive or negative lead.Type: ApplicationFiled: August 28, 2017Publication date: March 1, 2018Inventors: Srivatsan VENKATESAN, Tarkeshwar THAKUR, Vijayaragavan VENKATARATHINAM, Bhagirath GOUD, Pratheeswaran RAMASAMY
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Publication number: 20170091250Abstract: In an approach to save-to location selection, a computing device accesses a metadata file comprising a data table. The computing device successively checks the data table for entries that match a series of features of a file to be saved. If the computing device finds one or more matches, the computing device determines an associated save-to location. If the computing device does not find a match and has exhausted all of the series of features, the computing devices determines a default save-to location. The computing device receives a user selection based on or overriding the determination. The computing device updates the data table with information concerning each of the features of the file and information concerning the user selection.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: Anjil R. Chinnapatlolla, Vijai Kalathur, Rajaram B. Krishnamurthy, Ajay Sood, Srivatsan Venkatesan
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Publication number: 20170093767Abstract: In an approach to save-to location selection, a computing device accesses a metadata file comprising a data table. The computing device checks the data table for entries that match one or more features of a file to be saved, wherein each match is associated with a save-to location. The computing device computes confidence scores for each save-to location based on a predefined weight associated with to each feature. The computing device produces a list of recommended save-to locations based on the confidence scores. The computing device receives a user selection based on or overriding the recommendations. The computing device updates the data table with information concerning each of the features of the file and the user selection.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: Anjil R. Chinnapatlolla, Vijai Kalathur, Rajaram B. Krishnamurthy, Ajay Sood, Srivatsan Venkatesan