Abstract: An embodiment of this invention pertains to a digital circuit that shifts the phase of a clock signal. In this embodiment, multiple delay units, e.g., buffers, shift the clock signal multiple times and store a level of the clock signal within corresponding memory devices, e.g., flip-flops when triggered by the phase shifted clock signals. These levels may be at a high level (e.g., the clock signal has the value “1”) or a low level (e.g., the clock signal has the value “0”). A “phase selection table” stores multiple entries, each of the entries includes multiple clock level values. Each of the entries specifies values used to determine when the phase shifted clock signals transition from the high level to the low level. This transition point signifies a 180 degree phase shift. Using this transition point, other phase shifts can be determined.