Abstract: A high-mobility field-effect transistor, includes a stack along a Z axis, deposited on a substrate and comprising a buffer layer, a barrier layer, a heterojunction between the buffer layer and the barrier layer, and a two-dimensional electron gas localized in an XY plane perpendicular to the axis Z and in the vicinity of the heterojunction, a source, a drain, and a gate deposited on an upper face of the barrier layer, between the source and the drain, a first dielectric layer having a relative permittivity ?r and a thickness e which are such that: 0.5 nm?e/?r?2 nm, a metal pad arranged between the gate and the drain and deposited on the first dielectric layer, the metal pad being electrically connected to the gate.

Abstract: A power switching cell, and associated multi-level converter, include an input port capable of receiving a switching control signal, an input transistor linked by the gate to the input port, and by the source to a reference voltage, a self-biasing circuit comprising a self-biasing transistor linked by the gate to the drain of the input transistor, and a resistor connected in parallel between the gate and the source of the self-biasing transistor, and in series between the drain of the input transistor and the source of the self-biasing transistor, a power transistor, linked by the gate to the source of the self-biasing transistor and by the drain to a power supply voltage, and an isolating transistor linked by the gate and by the source to the gate and to the source of the power transistor, and by the drain to the output port of the cell.

Abstract: A power switching cell, and associated multi-level converter, include an input port capable of receiving a switching control signal, an input transistor linked by the gate to the input port, and by the source to a reference voltage, a self-biasing circuit comprising a self-biasing transistor linked by the gate to the drain of the input transistor, and a resistor connected in parallel between the gate and the source of the self-biasing transistor, and in series between the drain of the input transistor and the source of the self-biasing transistor, a power transistor, linked by the gate to the source of the self-biasing transistor and by the drain to a power supply voltage, and an isolating transistor linked by the gate and by the source to the gate and to the source of the power transistor, and by the drain to the output port of the cell.

Abstract: A transistor comprises a stack of semiconductor materials including, in particular, a first sub-layer, carefully arranged and with a specific thickness, splitting the buffer layer into two portions and including a third material so that the difference in the piezoelectric and spontaneous polarisation coefficients between the material of the buffer layer and the third material induces, at a first interface between the first portion of the buffer layer and the first sub-layer, a first fixed surface electric charge generating an electrical field directed along the axis z so as to follow the two-dimensional gas to be contained in the channel.

Abstract: A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.

Abstract: A stack along a z-axis for a high-electron-mobility field-effect transistor, comprises: a buffer layer comprising a first semiconductor material comprising a binary, ternary or quaternary nitride compound having a first bandgap, a barrier layer comprising a second semiconductor material comprising a binary, ternary or quaternary nitride compound and having a second bandgap, the second bandgap wider than the first bandgap, a heterojunction between the buffer and barrier layers and, a two-dimensional electron gas located in an XY plane perpendicular to the z-axis and in the vicinity of the heterojunction wherein: the buffer layer comprises a zone comprising fixed negative charges of density per unit volume higher than or equal to 1017 cm?3, the zone having a thickness smaller than or equal to 200 nm, the product of multiplication of the density per unit volume of fixed negative charges by the thickness of the zone between 1012 cm?2 and 3.1013 cm?2.

Abstract: A stack along a z-axis for a high-electron-mobility field-effect transistor, comprises: a buffer layer comprising a first semiconductor material comprising a binary, ternary or quaternary nitride compound having a first bandgap, a barrier layer comprising a second semiconductor material comprising a binary, ternary or quaternary nitride compound and having a second bandgap, the second bandgap wider than the first bandgap, a heterojunction between the buffer and barrier layers and, a two-dimensional electron gas located in an XY plane perpendicular to the z-axis and in the vicinity of the heterojunction wherein: the buffer layer comprises a zone comprising fixed negative charges of density per unit volume higher than or equal to 1017 cm?3, the zone having a thickness smaller than or equal to 200 nm, the product of multiplication of the density per unit volume of fixed negative charges by the thickness of the zone between 1012 cm?2 and 3.1013 cm?2.

Abstract: A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.