Abstract: Redefined hardware structured transactions and the associated responses in a data processing device are made user programmable. Three registers, a identifier register, a mask register and a response register, are used to redirect transactions or other operations within an application specific integrated circuit after post-silicon testing has been completed and there is no opportunity to redirect the hardware logic contained therein. When enabled, the registers allow for the insertion of blank table entries that can be programmed at a later time to handle unexpected output responses which occur due to unforeseen problems in the preprogrammed operation of the device. Transaction redirection can be accomplished on selected fields of identified transactions. The method is applicable to any hardware device in which it is desired to redirect actions originally defined in look-up tables when such tables are not capable of adjustment or alteration without redesign or re-manufacture.

Abstract: A method is provided for allocating system resources across multiple nodes of a system communicating through a hardware device. The method provides for allocation of transaction units or identifiers in an allocating component for use in a multiple target component which may be in a distinct target node within the multiple node system. Based on the operations or requests that a target node receives from multiple external request source nodes, each requiring the use of target transaction unit objects such as transaction identification bits, the method provides inclusion of such information in the initial request to a target node which allows any data transmission between the source node and the target node, or the target node and the source node to be accomplished without any further intervention by the allocating component. Such component may be a local memory control agent or device.

Abstract: Allocating potentially needed resources for a transaction before having completely received the transaction is disclosed. An initial part of a transaction is received in first clock cycle. The resources potentially needed by the transaction are determined based on the initial part thereof that has been received, and allocated. The transaction then proceeds. The final part of the transaction is received in a final clock cycle. The resources actually needed by the transaction from the resources previously allocated are determined based on the remaining part thereof that has been received. Any unneeded remaining resources are then deallocated.

Abstract: A method of classification of transaction address conflicts in a computer system for ensuring efficient ordering in a two-level snoopy cache architecture. The disclosure provides a method of classification and handling of address conflicts within a system to minimize the impact that address ordering places in a multiprocessor system with multiple memory control agents generating potentially conflicting addresses. A set of classification for each potential transaction conflict is provided against which decisions are provided which identifies the earliest point at which a subsequent transaction within the system may proceed to the same address identified by a previous transaction in the system. Classification of transactions are provided in several high level classes which define how such transactions within the system are handled based on the method disclosed.

Abstract: Allocating potentially needed resources for a transaction before having completely received the transaction is disclosed. An initial part of a transaction is received in first clock cycle. The resources potentially needed by the transaction are determined based on the initial part thereof that has been received, and allocated. The transaction then proceeds. The final part of the transaction is received in a final clock cycle. The resources actually needed by the transaction from the resources previously allocated are determined based on the remaining part thereof that has been received. Any unneeded remaining resources are then deallocated.

Abstract: Redefined hardware structured transactions and the associated responses in a data processing device are made user programmable. Three registers, a identifier register, a mask register and a response register, are used to redirect transactions or other operations within an application specific integrated circuit after post-silicon testing has been completed and there is no opportunity to redirect the hardware logic contained therein. When enabled, the registers allow for the insertion of blank table entries that can be programmed at a later time to handle unexpected output responses which occur due to unforeseen problems in the preprogrammed operation of the device. Transaction redirection can be accomplished on selected fields of identified tasctions. The method is applicable to any hardware device in which it is desired to redirect actions originally defined in look-up tables when such tables are not capable of adjustment or alteration without redesign or re-manufacture.

Abstract: A method of allocating hardware resources in a multiprocessor computer system which utilizes non-uniform memory access and distributed system resources across multiple nodes. The disclosure provides a method for allocating system resources across multiple nodes of a system communicating through a hardware device comprised of a tag and address crossbar system interconnecting node control devices. The method provides for allocation of transaction units or transaction identifiers in an allocating component for use in a multiple target component which may be in a distinct target node within the multiple node system.

Abstract: A method of classification of transaction address conflicts in a computer system for ensuring efficient ordering in a two-level snoopy cache architecture. The disclosure provides a method of classification and handling of address conflicts within a system to minimize the impact that address ordering places in a multiprocessor system with multiple memory control agents generating potentially conflicting addresses. A set of classification for each potential transaction conflict is provided against which decisions are provided which identifies the earliest point at which a subsequent trasaction within the system may proceed to the same address identified by a previous transaction in the system. Classification of transactions are provided in several high level classes which define how such transactions within the system are handled based on the method disclosed.

Abstract: A method of up-dating a cache (10) backed by a main memory (12). The cache is used as an intermediate high-speed memory between the main memory and a data processing unit (14). A burst mode request is for multiple words (k through n) included in an m-word line of data words (1 through m). The transfer takes place by first determining if the requested data words (k through n) reside in the cache. If they do, then the requested words (k through n) are transferred from the cache to the data processing unit. If they do not, then the requested words (k through n) are transferred simultaneously from the main memory both to the cache and to the data processing unit to thereby update the cache.

Abstract: Because of physical and electrical limitations, buffering of the clock in a data processing system often has to be provided by two different Integrated Circuit buffers. If the clock is connected in parallel to all buffer inputs (assuming that was within the clock drive capability) the outputs of one of the Integrated Circuits may be skewed or shifted in delay time relative to the outputs of the other integrated circuit, because of the differences in the buffers. Since, however, the delay times of all the buffers on each chip are nearly the same (to within a guaranteed tolerance typically) the circuit provided by this invention will give outputs all having small and predictable skews.

Abstract: A plurality of bus-coupler circuits (14) are connected to a bus wire (10) at different points (12) along its length. Each bus-coupler circuit (14) includes a conventional bus driver (22) which may, for example, comprise a relatively large transistor, but also a bus precharge circuit (16). The bus precharge circuit (16) in each bus-coupler circuit responds to a control signal (20) to apply a small, precharge pulse to the bus wire (10). The control signal (20) is applied to each of the bus-coupler circuits (22) in synchronism with the data (38) in such a way that electrical precharge pulses are applied to the bus wire (10) substantially simultaneously by each bus coupler at approximately the instant of time of an expected data signal transition. In this way, the bus wire (10) receives a small electrical charge (24) at the various points along its length at which the bus coupler circuits are connected. The bus is thereby precharged in anticipation of a transition.