Abstract: An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided.

Abstract: A phase locked loop arrangement (1) beamforming comprises two or more phase locked loops. The loops include a phase comparator (21, 22) and an adjustable charge pump arrangement (31, 32) having a loop filter (51, 52) and charge pump current source (41, 42) with an adjustment input (?adj) connected to the loop filter (51, 52) to inject an adjustable charge pump current into the loop filter. A constant current source (71, 72) is configured to inject a first predetermined charge current into the loop filter (51, 52). The adjustable charge pump arrangements (31, 32) are connected to the respective phase comparators (21, 22) to provide a voltage control signal (vctrl) to an oscillator (61, 62) of the respective phase adjustable phase locked loop (11, 12) in response to the respective control signal (up, down) and to generate a phase deviation between the first and one of the at least one second oscillator signals (fosc1, fosc2) based on an adjustment signal applied to the adjustment input (?adj).

Abstract: The programmable frequency control system presented herein provides frequency programmability and phase noise reduction for signals generated by a plurality of frequency programmable phase-locked loops (PLLs). In general, a modulated data stream input to each of the plurality of PLLs controls the frequency of the signal output by the PLLs. The solution presented herein reduces the phase noise by introducing a time shift to the modulated data stream applied to at least some of the PLLs so that at least some of the PLLs receive time-shifted versions of the modulated data stream relative to other PLLs. In so doing, the solution presented herein decorrelates the quantization noise generated by the plurality of frequency programmable PLLs.

Abstract: A voltage modulator (400) comprises a multi-level switched capacitor modulator (44) connected in parallel with a switched voltage regulator (42). An output of the multi-level switched capacitor modulator and an output of the switched voltage regulator are combined, or both connected to an output node, to generate an output voltage. The voltage modulator has an input node to receive at least one input signal and further comprises a control unit (46) arranged to control the switched voltage regulator and the multi-level switched capacitor modulator such that the output voltage follows the input signal.

Abstract: An analog phase-locked loop (PLL) is disclosed, comprising a voltage controlled oscillator (VCO); a frequency divider having its input connected to an output of the VCO; a first phase detector arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO.

Abstract: The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output signal at an output of the PLL responsive to a comparison between a reference signal input to the PLL and a feedback signal derived from the output signal. To control the phase of the output signal, a modulation signal is applied to one input of the oscillator, separate from the reference signal input, where the modulation signal comprises one or more pulses having a total area defined based on the desired phase shift. To maintain the desired phase shift at the output of the PLL, the PLL also sets a time relationship between the reference signal and the feedback signal based on the desired phase shift.

Abstract: A quadrature mixer arrangement is disclosed, which is adapted to translate an input signal by a translation frequency. The mixer arrangement is operated at a clock rate that equals the translation frequency times an oversampling rate, wherein the oversampling rate is not a multiple of four. The mixer arrangement comprises a sequence generator, at least one pair of mixers, and one or more correction networks. The sequence generator generates an in-phase mixer translation sequence and a quadrature-phase mixer translation sequence based on the oversampling rate. The in-phase mixer translation sequence is a time-discrete representation of a translation frequency sinusoidal function sampled at the clock rate, and the quadrature-phase mixer translation sequence is a time-discrete representation of the translation frequency sinusoidal function phase-shifted by ?/2 plus a phase deviation and sampled at the clock rate, wherein the phase deviation is a function of the oversampling rate.

Abstract: A circuit for calibration measurements comprises a first and a second current source arranged to provide current outputs; a resistor connected between the first current source and a reference voltage; a capacitor connected between the second current source and the reference voltage; a discharge switch connected in parallel with the capacitor and arranged to selectively discharge the capacitor; a comparator circuit arranged to compare voltages across the resistor and the capacitor and output a signal when voltage across the capacitor reaches the voltage across the resistor; and a controller having a clock signal input and connected to the output of the comparator circuit.

Abstract: The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output signal at an output of the PLL responsive to a comparison between a reference signal input to the PLL and a feedback signal derived from the output signal. To control the phase of the output signal, a modulation signal is applied to one input of the oscillator, separate from the reference signal input, where the modulation signal comprises one or more pulses having a total area defined based on the desired phase shift. To maintain the desired phase shift at the output of the PLL, the PLL also sets a time relationship between the reference signal and the feedback signal based on the desired phase shift.

Abstract: The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output signal at an output of the PLL responsive to a comparison between a reference signal input to the PLL and a feedback signal derived from the output signal. To control the phase of the output signal, a modulation signal is applied to one input of the oscillator, separate from the reference signal input, where the modulation signal comprises one or more pulses having a total area defined based on the desired phase shift. To maintain the desired phase shift at the output of the PLL, the PLL also sets a time relationship between the reference signal and the feedback signal based on the desired phase shift.

Abstract: The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output signal at an output of the PLL responsive to a comparison between a reference signal input to the PLL and a feedback signal derived from the output signal. To control the phase of the output signal, a modulation signal is applied to one input of the oscillator, separate from the reference signal input, where the modulation signal comprises one or more pulses having a total area defined based on the desired phase shift. To maintain the desired phase shift at the output of the PLL, the PLL also sets a time relationship between the reference signal and the feedback signal based on the desired phase shift.

Abstract: A quadrature mixer arrangement is disclosed, which is adapted to translate an input signal by a translation frequency. The mixer arrangement is operated at a clock rate that equals the translation frequency times an oversampling rate, wherein the oversampling rate is not a multiple of four. The mixer arrangement comprises a sequence generator, at least one pair of mixers, and one or more correction networks. The sequence generator generates an in-phase mixer translation sequence and a quadrature-phase mixer translation sequence based on the oversampling rate. The in-phase mixer translation sequence is a time-discrete representation of a translation frequency sinusoidal function sampled at the clock rate, and the quadrature-phase mixer translation sequence is a time-discrete representation of the translation frequency sinusoidal function phase-shifted by ?/2 plus a phase deviation and sampled at the clock rate, wherein the phase deviation is a function of the oversampling rate.

Abstract: An analog phase-locked loop (PLL) is disclosed, comprising a voltage controlled oscillator (VCO); a frequency divider having its input connected to an output of the VCO; a first phase detector arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO.

Abstract: A voltage modulator (400) comprises a multi-level switched capacitor modulator (44) connected in parallel with a switched voltage regulator (42). An output of the multi-level switched capacitor modulator and an output of the switched voltage regulator are combined, or both connected to an output node, to generate an output voltage. The voltage modulator has an input node to receive at least one input signal and further comprises a control unit (46) arranged to control the switched voltage regulator and the multi-level switched capacitor modulator such that the output voltage follows the input signal.

Abstract: An analog phase-locked loop, PLL, (100, 200) is disclosed, comprising a voltage controlled oscillator (102, 202); a frequency divider (104, 204) having its input connected to an output of the VCO; a first phase detector (106, 206) arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump (108, 208) connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter (110, 210) connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO.

Abstract: An analog phase-locked loop, PLL, (100, 200) is disclosed, comprising a voltage controlled oscillator (102, 202); a frequency divider (104, 204) having its input connected to an output of the VCO; a first phase detector (106, 206) arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump (108, 208) connected to an output of the first phase detector and arranged to divider output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter (110, 210) connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO.

Abstract: The teachings presented herein allow the same sequence of local oscillator waveform sample values to be used for driving two harmonic rejection mixers for which quadrature operation is desired, irrespective of whether the oversampling rate of the sequence is divisible by four or only divisible by two. This ability is obtained by controlling whether the quadrature mixer clocks coincidentally with the in-phase mixer, or clocks a half clock cycle out of phase relative to the in-phase mixer. Several advantages attend the contemplated circuit arrangement and method of operation. Example advantages include the improved matching that comes from operating both mixers with the identical waveform sample values, and the improved flexibility in optimizing the harmonic rejection and/or interference-related operation of the mixers over a broader range of frequencies of interest, which flows from having a larger set of usable OSRs.

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC), a second DAC, and a control circuit to select which DAC to use for digital-to-analog conversion of a digital signal. Concerned with the noise level produced at a given out-of-band frequency, the control circuit bases its selection of DACs, at least in part, on a frequency distance between the given out-of-band frequency and the digital signal's frequency. The control circuit, for example, may select the DAC producing the lowest noise level at that frequency distance, or, if both DACs are able to reduce noise to a level below a noise tolerance specified for the frequency distance, the DAC consuming the least power. To reduce the chip area required for the digital-to-analog conversion circuit, the first and second DACs advantageously have topologies that permit them to share common components (e.g., DAC unit elements).

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC), a second DAC, and a control circuit to select which DAC to use for digital-to-analog conversion of a digital signal. Concerned with the noise level produced at a given out-of-band frequency, the control circuit bases its selection of DACs, at least in part, on a frequency distance between the given out-of-band frequency and the digital signal's frequency. The control circuit, for example, may select the DAC producing the lowest noise level at that frequency distance, or, if both DACs are able to reduce noise to a level below a noise tolerance specified for the frequency distance, the DAC consuming the least power. To reduce the chip area required for the digital-to-analog conversion circuit, the first and second DACs advantageously have topologies that permit them to share common components (e.g., DAC unit elements).

Abstract: According to an embodiment of a time to digital converter, the time difference between a signal of interest and a reference signal is measured by operating a digitally controlled oscillator at a first frequency during a first portion of the reference signal period and changing the operating frequency from the first frequency to a second frequency during the reference signal period as a function of the time difference between the signal of interest and the reference signal. The time to digital converter continuously counts how many signal transitions occur at an output of the digitally controlled oscillator during the reference signal period. The time difference between the signal of interest and the reference signal is estimated based on the number of signal transitions counted during the reference signal period.