Abstract: A direct memory access (DMA) circuit includes a first register for storing an address for the transfer of data, apparatus for transferring data at sequential addresses beginning at the address in the first register until all data at sequential addresses has been transferred, a second register for storing a beginning address for a list of addresses, and a state machine which responds to the completion of a transfer of data at sequential addresses beginning at the address in the first register and an indication that more data is to be transferred to transfer an address from the list at the address in the second register to the first register and causes the apparatus for transferring data to commence.

Abstract: A data processing system includes a processor coupled to a system bus. A memory controller is also coupled to the system bus and to a memory bus in communication with a plurality of single in-line memory modules (SIMMs). Each SIMM comprises a plurality of DRAMS coupled to four cross bar switches (CBSs), such that address and data information is provided to the DRAMs through the cross bar switches. Each CBS includes a counter and decoder which controls a multiplexor. The multiplexor is coupled to enable ID logic, and four input registers (A.sub.R, B.sub.R, C.sub.R, D.sub.R), such that register A.sub.R is coupled to the output of the multiplexor, and the remaining registers are coupled to the input side of the multiplexor. An input buffer on the CBS is coupled to four input registers (A'.sub.W, B'.sub.W, C'.sub.W, D.sub.W). In addition, three of the input registers (A'.sub.W, B'.sub.W, C'.sub.W) are coupled to intermediate input registers A.sub.W, B.sub.W and C.sub.W.