Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.

Abstract: A configurable logic array composed of: a multiplicity of logic cells, each containing look-up tables, a multiplicity of customizable I/O cells, each containing a multiplicity of pads; and a customizable via connection layer for customizing the cells and interconnect between them, may be constructed to include the option of customizing the I/O cells to act as power or ground pins. Assigning custom power and ground pins may depend on the types of I/O cells and package bonding options.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.

Abstract: The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.

Abstract: An embedded redistribution interposer is disclosed for providing footprint compatible chip package migration in which a die designed to be mounted into chip package is originally implemented using a first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package. According to the present invention, the embedded redistribution interposer includes a substrate having a plurality of bond pads on a top side thereof, wherein the redesigned die is mounted to the top of the interposer substrate, and the bottom of the interposer substrate is mounted to the substrate of the chip package. The redesigned die is connected to the redistribution interposer via a first set of electrical connections coupled between the die and the interposer bond pads.

Abstract: The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.

Abstract: A system and method are provided for forming a multi-chip package. The multi-chip package includes a multi-layer substrate and a heat spreader of single, unibody construction. At least two integrated circuits are coupled between the multi-layer substrate and the heat spreader. The integrated circuits are spaced from one another to allow airflow between those circuits and a portion of the underside surface of the heat spreader. Depending on the layout of the package, a passive device can also be placed in the space between integrated circuits. The passive device extends upward a spaced distance from the underneath surface of the heat spreader so as not to block the airflow therebetween. The multi-chip package can accommodate integrated circuits that are either all packaged, all unpackaged, or a combination of each.

Abstract: An embedded redistribution interposer is disclosed for providing footprint compatible chip package migration in which a die designed to be mounted into chip package is originally implemented using a first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package. According to the present invention, the embedded redistribution interposer includes a substrate having a plurality of bond pads on a top side thereof, wherein the redesigned die is mounted to the top of the interposer substrate, and the bottom of the interposer substrate is mounted to the substrate of the chip package. The redesigned die is connected to the redistribution interposer via a first set of electrical connections coupled between the die and the interposer bond pads.