Patents by Inventor Stanford W. Crane, Jr.

Stanford W. Crane, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6577003
    Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: June 10, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
  • Patent number: 6574726
    Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: June 3, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventor: Stanford W. Crane, Jr.
  • Patent number: 6554651
    Abstract: An electrical interconnect system includes an insulative substrate, and a plurality of groups of electrically conductive contacts arranged on the substrate. The contacts are electrically isolated from one another, and the groups are interleaved among one another in a nested configuration. The system also includes a plurality of receiving-type interconnect components each for receiving one of the groups of contacts within that component. The nested configuration of the groups of contacts maintains the contacts in close proximity to one another and, at the same time, allows adequate clearance between the contacts so that each group may be received within one of the receiving-type interconnect components.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: April 29, 2003
    Inventor: Stanford W. Crane, Jr.
  • Patent number: 6475832
    Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: November 5, 2002
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li
  • Patent number: 6461197
    Abstract: An electrical connector includes a male connector and a female connector. The female connector includes a female connector housing and a plurality of female contact pins. The female contact pins includes a contact portion, a stabilizer portion, and a tail portion. The contact portion extends from the stabilizer portion at an angle. A lateral distance spanned by the angled contact portion is substantially the same as or less than the width of the stabilizer portion in the same direction. The female contact pins are arranged on the female connector housing in clusters of four. The clusters are arranged in rows such that each pair of rows defines five rows of female contact pins. The male connector includes a male connector housing and a plurality of male contact pins. The male connector housing has a plurality of buttresses extending therefrom. The male contact pins are arranged on the male connector housing to correspond to the arrangement of female contact pins.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: October 8, 2002
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
  • Publication number: 20020117751
    Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.
    Type: Application
    Filed: May 31, 2001
    Publication date: August 29, 2002
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata, Ton-Yong Wang, Andreas C. Cangellaris, Jose Schutt-Aine
  • Patent number: 6421254
    Abstract: A multi-chip module includes a housing having insulative side walls and an end plate, conductive leads extending from the side walls, integrated circuit (IC) dies mounted to the end plate, and one or more interconnect dies mounted to the end plate. The end plate is made from a heat sink material, such as copper. Each interconnect die is positioned between a pair of the IC dies. Electrically conductive material connects the IC dies to the interconnect die, connects the IC dies to the conductive leads, and connects the interconnect dies to the conductive leads. The interconnect dies function to interconnect the IC dies and to interconnect the IC dies to the conductive leads. The interconnect die may be embodied by wiring layers formed on a silicon substrate.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: July 16, 2002
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li, Moises Behar, Dan Fuoco, Bill Ahearn
  • Patent number: 6339191
    Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: January 15, 2002
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
  • Patent number: 6334794
    Abstract: A male connector connects with a female connector to establish an electrical connection. The male and female connectors each include a connector housing having hold-down tabs at opposite ends thereof for securing the connector housing to a substrate. The hold-down tabs are staggered or diagonally located such that one hold-down tab is proximal a first side of the connector housing and the other hold-down is proximal a second side of the connector housing. The staggered or diagonally-located hold-down tabs stabilize the connector housing against rocking or other movement on the substrate. The arrangement of hold-down tabs also permits the connector housing to nest or merge with another similarly-designed connector housing. The nested or merged connector housing conserve substrate space and permit a higher density of contacts in a given space on the substrate, whether the space is at an edge or in an interior of the substrate.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: January 1, 2002
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
  • Patent number: 6307258
    Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: October 23, 2001
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li
  • Patent number: 6305987
    Abstract: An integrated module includes a connector for detachable connection to a signal source, with the connector having internal electrically conductive pins, and a housing defining a cavity for holding at least one semiconductor die. The housing includes side walls and an end plate joined to the side walls. Electrically conductive leads extend through at least one of the side walls with each of the leads including an internal lead section extending within the cavity and an external lead section extending externally of the cavity through at least one side wall. One of the side walls of the housing includes a portion that is attached to the connector, with the side walls and a bottom part of the connector being formed as one integrally molded part or as two separate parts that are joined together using processes such as ultrasonic welding.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: October 23, 2001
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta
  • Patent number: 6266246
    Abstract: A multi-chip module includes a housing having insulative side walls and an end plate, conductive leads extending from the side walls, integrated circuit (IC) dies mounted to the end plate, and one or more interconnect dies mounted to the end plate. The end plate is made from a heat sink material, such as copper. Each interconnect die is positioned between a pair of the IC dies. Electrically conductive material connects the IC dies to the interconnect die, connects the IC dies to the conductive leads, and connects the interconnect dies to the conductive leads. The interconnect dies function to interconnect the IC dies and to interconnect the IC dies to the conductive leads. The interconnect die may be embodied by wiring layers formed on a silicon substrate.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: July 24, 2001
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li, Moises Behar, Dan Fuoco, Bill Ahearn
  • Patent number: 6247972
    Abstract: An electrical connector includes a male connector and a female connector. The female connector includes a female connector housing and a plurality of female contact pins. The female contact pins includes a contact portion, a stabilizer portion, and a tail portion. The contact portion extends from the stabilizer portion at an angle. A lateral distance spanned by the angled contact portion is substantially the same as or less than the width of the stabilizer portion in the same direction. The female contact pins are arranged on the female connector housing in clusters of four. The clusters are arranged in rows such that each pair of rows defines five rows of female contact pins. The male connector includes a male connector housing and a plurality of male contact pins. The male connector housing has a plurality of buttresses extending therefrom. The male contact pins are arranged on the male connector housing to correspond to the arrangement of female contact pins.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: June 19, 2001
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
  • Patent number: 6203347
    Abstract: An electrical connector includes a projection-type interconnect component and a receiving type interconnect component. The projection-type interconnect component includes an insulative buttress and a plurality of electrically conductive contacts. The contacts are spaced from each other around a circumference of the insulative buttress. The receiving-type interconnect component is adapted for receiving the projection-type interconnect component. The receiving-type interconnect component includes a plurality of flexible, electrically conductive contacts and a spacer movable relative to the flexible contacts. The spacer at least partially flexes the flexible contacts when the spacer is in a first position. The insulative buttress of the projection-type interconnect component displaces the spacer of the receiving-type interconnect component when the projection-type interconnect component is received by the receiving-type interconnect component.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: March 20, 2001
    Assignee: Silicon Bandwidth Inc.
    Inventor: Stanford W. Crane, Jr.
  • Patent number: 6141869
    Abstract: A lead insertion machine includes a substrate supply, a conductive lead supply, and an lead insertion mechanism. The conductive leads are inserted into lead passages formed in side walls of the substrate. Also disclosed is a method of manufacturing a semiconductor die carrier including the steps of forming a plurality of conductive leads, forming a substrate for holding a semiconductor die, the substrate having a plurality of insulative side walls defining an exterior surface of said substrate, each of the side walls having a plurality of lead passages formed therethrough, and simultaneously inserting at least one of the conductive leads into the lead passage of one of the side walls for retention therein and at least one other of the conductive leads into the lead passage of another of the side walls for retention therein.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: November 7, 2000
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Daniel Larcomb, Lakshminarasimha Krishnapura
  • Patent number: 6097086
    Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts. A semiconductor die carrier may also include an insulative substrate; a plurality of leads each having an external portion extending out of the semiconductor die.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: August 1, 2000
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
  • Patent number: 6092139
    Abstract: A computer system includes a bus system having a local bus unit, a memory bus unit, an input/output bus unit, and an expansion bus unit. A pluggable central processing unit circuit board includes a microprocessor, a pluggable memory circuit board coupled to the central processing unit circuit board through the memory bus unit, and a pluggable bridge circuit board coupled to the central processing unit circuit board. A plurality of connectors includes a first connector unit for receiving the pluggable central processing unit circuit board; a second connector unit for receiving the pluggable memory circuit board; and a third connector unit for receiving the pluggable bridge circuit board. The third connector unit is coupled to the first connector unit of the central processing unit circuit board through the bus system. A plurality of peripheral devices are coupled to the bridge circuit board through the input/output bus unit.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: July 18, 2000
    Inventors: Stanford W. Crane, Jr., Bruce A. Smith, Edward R. Vanderslice
  • Patent number: 6078102
    Abstract: A semiconductor die package includes a housing and a plurality of leads extending through openings in the housing. The package is designed to be mounted to a printed circuit board in both a horizontal configuration and in an upright configuration. In the horizontal configuration, the face of the die is held parallel to the surface of the printed circuit board. An edge of the die faces the printed circuit board when the package is mounted in an upright configuration. The leads are L-shaped so that either an end surface or an outer side surface of the lead can be surface mounted to the printed circuit board. The leads may extend from only one side wall of the housing. In this case, the housing may include a standoff on a bottom surface adjacent a side wall opposite the leads to balance the housing. Alternatively, stabilizing leads may be provided from the opposite side wall to improve horizontal mounting stability.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: June 20, 2000
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura
  • Patent number: D447143
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: August 28, 2001
    Assignee: Silicon Bandwidth
    Inventors: Stanford W. Crane, Jr., Moises Behar, Kevin J. Link, Daniel J. Michalski
  • Patent number: D430565
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: September 5, 2000
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Kevin J. Link, Daniel J. Michalski, Moises Behar