Abstract: An output buffer is provided, to which first and second input signals are applied and that delivers an output signal. The output buffer includes a second offset switching stage installed in cascade downstream from a first switching stage. The second offset switching stage generates control points shifted in time with respect to memory points.

Abstract: A device for generation of a reference frequency includes a component configured for generating a reference voltage, and a slaving circuit configured for slaving the reference frequency to the reference voltage.

Abstract: The disclosure relates to an electronic circuit including at least one first and one second differential pair each including a plurality of transistors. All the transistors of said first and second differential pair are included in a single well.

Abstract: An output interfacing device is provided, which receives at its input an input signal and provides at its output, an output signal to an external load. The output interfacing device invertes the effect of the capacitance of the external load on the slew rate of the output signal.

Abstract: An output buffer is provided, to which first and second input signals are applied and that delivers an output signal. The output buffer includes a second offset switching stage installed in cascade downstream from a first switching stage. The second offset switching stage generates control points shifted in time with respect to memory points.

Abstract: A device for generation of a reference frequency includes a component configured for generating a reference voltage, and a slaving circuit configured for slaving the reference frequency to the reference voltage.

Abstract: The disclosure relates to an electronic circuit including at least one first and one second differential pair each including a plurality of transistors. All the transistors of said first and second differential pair are included in a single well.

Abstract: The disclosure relates to an electronic circuit including at least one first differential pair including first and second transistors. The first and second transistors share one and the same single source or one and the same single drain.

Abstract: An electronic circuit is provided, which includes a dual supply having a first supply for a first portion of said circuit and a second supply for a second portion of said circuit. The electronic circuit further includes a protection circuit for protecting at least one transistor of said first portion. The protection circuit includes a first protection transistor of which the drain is connected to a connection between said first portion and said second portion and the gate is connected to said first power supply. A voltage reducer reduces the voltage between the drain and the gate of said first protection transistor.