Abstract: A system and method for efficient matching regular expression patterns across multiple packets. A deep packet inspection system can be embodied in a switch ASIC using a flow tracker and a signature matching engine. The flow tracker can be positioned in an ingress portion of the switch ASIC at a location where packets in a bi-direction flow can be observed and recorded. The flow tracker generates a signature match request that is forwarded to a signature matching engine in an auxiliary pipeline. The signature matching engine is enabled to perform cross-packet signature matching using signature matching state machines and reports the signature matching results to the flow tracker using a response packet that is sent to the ingress pipeline.

Abstract: A system and method for efficient matching regular expression patterns across multiple packets. A deep packet inspection system can be embodied in a switch ASIC using a flow tracker and a signature matching engine. The flow tracker can be positioned in an ingress portion of the switch ASIC at a location where packets in a bi-direction flow can be observed and recorded. The flow tracker generates a signature match request that is forwarded to a signature matching engine in an auxiliary pipeline. The signature matching engine is enabled to perform cross-packet signature matching using signature matching state machines and reports the signature matching results to the flow tracker using a response packet that is sent to the ingress pipeline.

Abstract: A system and method for integrating line-rate application recognition in a switch ASIC. Switching platforms can be built using this feature with a conventional control plane processor rather than a more expensive specialized processor. A deep packet inspection system can be embodied in a switch ASIC using a flow tracker and a signature matching engine. The flow tracker can be positioned in an ingress portion of the switch ASIC at a location where packets in a bi-direction flow can be observed and recorded. The flow tracker generates a signature match request that is forwarded to a signature matching engine in an auxiliary pipeline. The signature matching engine analyzes packets using signature matching state machine and reports the signature matching results to the flow tracker using a response packet that is sent to the ingress pipeline.

Abstract: A system and method for efficient matching regular expression patterns across multiple packets. A deep packet inspection system can be embodied in a switch ASIC using a flow tracker and a signature matching engine. The flow tracker can be positioned in an ingress portion of the switch ASIC at a location where packets in a bi-direction flow can be observed and recorded. The flow tracker generates a signature match request that is forwarded to a signature matching engine in an auxiliary pipeline. The signature matching engine is enabled to perform cross-packet signature matching using signature matching state machines and reports the signature matching results to the flow tracker using a response packet that is sent to the ingress pipeline.

Abstract: A system and method for efficient matching regular expression patterns across multiple packets. A deep packet inspection system can be embodied in a switch ASIC using a flow tracker and a signature matching engine. The flow tracker can be positioned in an ingress portion of the switch ASIC at a location where packets in a bi-direction flow can be observed and recorded. The flow tracker generates a signature match request that is forwarded to a signature matching engine in an auxiliary pipeline. The signature matching engine is enabled to perform cross-packet signature matching using signature matching state machines and reports the signature matching results to the flow tracker using a response packet that is sent to the ingress pipeline.

Abstract: A system and method for integrating line-rate application recognition in a switch ASIC. Switching platforms can be built using this feature with a conventional control plane processor rather than a more expensive specialized processor. A deep packet inspection system can be embodied in a switch ASIC using a flow tracker and a signature matching engine. The flow tracker can be positioned in an ingress portion of the switch ASIC at a location where packets in a bi-direction flow can be observed and recorded. The flow tracker generates a signature match request that is forwarded to a signature matching engine in an auxiliary pipeline. The signature matching engine analyzes packets using signature matching state machine and reports the signature matching results to the flow tracker using a response packet that is sent to the ingress pipeline.

Abstract: The invention provides a method for utilizing the Inter Packet Gaps (IPGs) to create an Extended Link Monitoring Channel in a physical layer transceiver for a 10 Gb/s Ethernet link for communicating link related information, thus providing an extensive link maintenance capability. A corresponding transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising a physical coding sublayer (PCS) extension circuit for implementing the Extended Link Monitoring Channel is also provided.

Abstract: A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three closely spaced sampling points of the eye, and compares advanced and delayed sampled data with the nominal sampled data. If either the advanced or delayed sampled data differ from the nominal sampled data, i.e. if advanced or delayed errors are detected, a shift in the sampling edge position may be required. A logic circuit performs a method determining the occurrence of advanced or delayed errors over progressively longer time intervals, and to adjust the sampling edge position of the CDR by controlling the phase offset.

Abstract: The invention provides a method for utilizing the Inter Packet Gaps (IPGs) to create an Extended Link Monitoring Channel in a physical layer transceiver for a 10 Gb/s Ethernet link for communicating link related information, thus providing an extensive link maintenance capability. A corresponding transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising a physical coding sublayer (PCS) extension circuit for implementing the Extended Link Monitoring Channel is also provided.

Abstract: A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three closely spaced sampling points of the eye, and compares advanced and delayed sampled data with the nominal sampled data. If either the advanced or delayed sampled data differ from the nominal sampled data, i.e. if advanced or delayed errors are detected, a shift in the sampling edge position may be required. A logic circuit performs a method determining the occurrence of advanced or delayed errors over progressively longer time intervals, and to adjust the sampling edge position of the CDR by controlling the phase offset.

Abstract: The invention provides a method for utilizing the Inter Packet Gaps (IPGs) to create an Extended Link Monitoring Channel in a physical layer transceiver for a 10 Gb/s Ethernet link for communicating link related information, thus providing an extensive link maintenance capability. A corresponding transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising a physical coding sublayer (PCS) extension circuit for implementing the Extended Link Monitoring Channel is also provided.