Abstract: A disk drive element lapping system with closed loop feedback comprising a row of a plurality of disk drive elements and a lapping plate for lapping the plurality of disk drive elements. A plurality of current sources is included, each of which applies a current to a respective one of the plurality of disk drive elements. A coil for applying an alternating magnetic field to the plurality of disk drive elements. A plurality of monitors is included, each of which monitors the voltage across a respective one of the plurality of disk drive elements in response to the direct current and the alternating magnetic field. A processor determines the magnetic responsiveness of each of the plurality of disk drive elements based on the monitored voltage.

Abstract: A PCI and PCI-X bus-bridging method and apparatus is described. Posted memory write requests and requests not allowed to execute before a prior posted memory write are written to one queue. Requests that are allowed to pass a posted memory write are written to a separate second queue. Requests at the head of these queues receiving a RETRY response or failing to execute completely are removed from the queue and stored in a Retry List. Requests execute depending on which one of them wins control of the destination bus. The posted memory writes queue and any request not allowed to pass a posted memory write are blocked from executing if there is a location in the Retry List occupied by a posted memory write.

Abstract: A PCI and PCI-X bus-bridging method and apparatus is described. Posted memory write requests and requests not allowed to execute before a prior posted memory write are written to one queue. Requests that are allowed to pass a posted memory write are written to a separate second queue. Requests at the head of these queues receiving a RETRY response or failing to execute completely are removed from the queue and stored in a Retry List. Requests execute depending on which one of them wins control of the destination bus. The posted memory writes queue and any request not allowed to pass a posted memory write are blocked from executing if there is a location in the Retry List occupied by a posted memory write.

Abstract: A row of disk drive slider blanks with magneto-resistive read sensors are lapped after being mounted on the flat surface of a row carrier used to mount the row assembly on a row bending tool. Residual stresses present in the row due to wafer processing are relieved by removing the kerf areas between the slider blanks prior to lapping to prevent the stresses from causing inaccuracies in the lapping process. The stability of sliders below 30% can be enhanced by using wafers thicker than is required and then slicing the extra material from the row of slider blanks after it has been bonded to the row carrier either before or after the lapping process.

Abstract: An improved SRTS clock recovery system of a network node that adjusts the range of a received source RTS sample and a locally generated destination RTS sample to compensate for inherent characteristics of a network system. In addition, the improved system extends the range of the RTS samples to properly interpret large phase differences between a source node clock and transmit clock generated by the network node. This novel technique for interpreting source and destination RTS samples enables the improved network node to accurately recover a source clock frequency from a network transmission in a highly stressed network system. Specifically, the SRTS clock recovery system includes an RTS sample interpreter having a slope determinator for determining the expected average change in source and destination RTS samples over time.

Abstract: A destination station receives from a network a data packet that is transmitted as a plurality of cells and separately encodes each of the received cells, to produce associated, individual c-bit partial CRC remainders, where c is the number of bits in the CRC remainder associated with the packet. These partial CRC remainders correspond to the respective contributions that the cells make to the packet CRC pattern. The encoder appends the partial CRC remainders to the cells, and the station then stores them in an associated memory and links the individual cells to previously stored cells from the same packet with pointers. Once all the cells of a packet are encoded and stored, the destination station retrieves appended partial CRC remainders from the memory, and provides the remainders to a partial CRC encoder. The encoder manipulates the partial remainders and produces a packet CRC remainder.

Abstract: A magnetic resistive head lapping system is disclosed herein which incorporates an automatic applied force lapping fixture for row tool balance and bow correction. The fixture is mounted over a rotatable lapping plate and is effective to present a row tool or slider bar with magnetic heads deposited thereon to the abrasive surface of the lapping plate in proper orientation during batch fabrication of the magnetic heads. The fixture includes a stationary assembly and a movable assembly on which the row tool and slider bar are carried. A pair of electromagnetic actuators on the stationary assembly correct for balance while three electromagnetic coils on the movable assembly correct for row tool bow.

Abstract: An adjustable row or transfer tool is disclosed herein compensating for row bow or distortion during a lapping process on a surface so as to establish uniform and substantially precise throat heights for a plurality of thin film transducers carried on a row of magnetic head sliders. To provide for adjustment, the body of the row tool is a double series of relief slots provided in an edge marginal region immediately adjacent to the surface intended to be lapped. The first series includes elongated relief slots disposed between square shaped slots extending across the length of the tool while the second series includes several relief slit openings across the tool length above the first series to terminate in cavities at each end. Bend holes in the tool body are located between the first and second series of relief slots and slits. Adjustment may be achieved by mounting the row tool to a closed loop lapping system.

Abstract: The classifier device disclosed herein analyzes message headers of the type which comprise a sequence of bit groups presented successively. The device employs a read/write memory for storing at a multiplicity of addresses, an alterable parse graph of instructions. The parse graph instructions include node instructions which comprise opcodes in association with respective next address characterizing data and terminator instructions which comprise identifying data for previously characterized header types. A logical processor responds to a node instruction read from memory either by initiating another memory read at a next address which, given the current state of the processor, is determinable from the current node instruction and the current header bit group or by outputting data indicating recognition failure if no next address is determinable. The logical processor responds to a terminator instruction by outputting respective header identifying data.

Abstract: A memory subsystem including a read-only memory (ROM), a random access read/write memory (RAM) and a selection system for selecting the output of one of the memories for use by downstream circuitry. The selection of the output is based on input address signals so that the contents of the RAM can substitute for the contents of selected locations in the ROM. If a substitution is to be made, an entry is made in a content addressable memory, which stores addresses for which the RAM output is to be substituted for ROM output. A test system is provided to verify the contents of the content addressable memory.

Abstract: A bus interface unit for connecting a processor to a memory to form a digital data processing system. The storage locations in the memory are grouped in pages each having a selected access rights mode which regulates access to the data stored therein by the programs, each of which has a selected access rights mode. The access rights are assigned on a page by page basis. If an access request from a program requires transfers to multiple locations, the processor will normally perform an access verification on the first location while it is in the first transfer operation, and then perform the transfer operation and successive transfer operations. If the transfer operations require accesses to separate pages in memory, a microtrap operation is performed and the processor performs access verifications on locations in both pages before performing any transfers.

Abstract: One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68).

Abstract: A special instruction processor, such as a floating point accelerator processor, that processes a special class of instructions. Each instruction identifies the number of operands to be processed as well as the number of data words required to be transferred for each operand. The central processing unit retrieves and decodes each instruction, and transfers the special instructions to the special instruction processor. Both processors decode the special instructions to determine the numbers of operands and data words to be transferred. The central processing unit retrieves the data words from memory and transmits them to the special instruction processor. The special instruction processor processes the instruction and signals the central processor when finished. The central processor then causes the special instruction processor to transmit the processed data back to the central instruction processor.

Abstract: A special instruction processor that connects to a central processing unit in a data processing system. The central processing unit processes a number of instructions. Instructions involving operands first retrieve the operands from memory, from general purpose registers in the central processor or the instruction stream. These operands are transferred to the special instruction processor. If the instruction is one of a predetermined set of instructions that is executed by the special instruction processor, the special instruction processor will, upon receiving the operands, generate an overriding signal that alters the operation of the central processor unit by inhibiting its processing of the operands. Instead, the special instruction processor unit, that is specifically designed to perform the operations efficiently, computes a result.