Abstract: A multi-threshold optical binning method for classifying the image quality of an optical sensor is presented. In accordance with the invention, a sensor tester causes a sensor pixel image to be generated by a sensor under test. The sensor pixel image is comprised of a plurality of pixels, each represented by an associated quantized intensity level. The quantized intensity level of a pixel may fall into one of a first pixel class, a second pixel class, or a third pixel class, for example, a dark pixel class, a dim pixel class, and an acceptable pixel class. An image filter processes the sensor pixel image, filtering but all pixels that fall within the acceptable pixel class, to generate a defective pixel map. The defective pixel map includes those pixels which have a quantized intensity level that falls within the first and/or second pixel class but not the third pixel class.

Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H2O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.

Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H.sub.2 O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.

Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a long, narrow collector region. An N-type collector is implanted in the collector region. The implants are diffused to form a shallow gradient P-N junction. Then, device features requiring a predetermined spacing and size are photolithographically defined along the length of the collector region. The device features and the collector region are made long enough for the features to readily transect the collector region even if the mask is misaligned. The active transistor and the collector, base and emitter contacts are self-aligned with the collector region so as to take advantage of the noncritical spacing of the preceding steps. A single polysilicon layer used to form base, collector and emitter contacts and a triple diffusion transistor.