Patents by Inventor Stanley D. Harder

Stanley D. Harder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAG
    Patent number: 6205560
    Abstract: A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the stream of instructions matching the instruction or data breakpoint stored in the set of debug registers and a debug configuration register for enabling transfer of program control to one of a plurality of destinations in response to the debug exception. The debug configuration registers may designate system management mode, JTAG routine or a software debug interrupt handler as the destination.
    Type: Grant
    Filed: February 27, 1996
    Date of Patent: March 20, 2001
    Assignee: VIA-Cyrix, Inc.
    Inventors: Mark W. Hervin, Mark W. Bluhm, Stanley D. Harder, William C. Patton
  • Integrated circuit extraction tool
    Patent number: 5617628
    Abstract: An integrated circuit extraction tool for extracting sockets or microprocessors having a staggered pin grid array (SPGA) pin arrangement. Such tool includes an elongated base having a first end and a second end, each end forming a set of teeth that permit entry and extension of the teeth, diagonally, through the staggered pins of the socket or microprocessor. In the preferred embodiment, the first end is disposed at ninety degree with respect to the elongated base. Further, the elongated base is formed with a curvature to enhance the leverage action necessary for an extraction operation.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: April 8, 1997
    Assignee: Cyrix Corporation
    Inventors: Stanley D. Harder, Thomas D. Selgas, Jr.
  • Method and apparatus determining order and identity of subunits by inputting bit signals during first clock period and reading configuration signals during second clock period
    Patent number: 5594925
    Abstract: A unit train (10) includes a base unit (12). Base unit (12) generates a clock signal and a bit signal. Base unit (12) also receives and interprets a data signal. Unit train (10) also includes a plurality of subunits (14) serially coupled in a certain order. Each subunit (14) receives the clock signal and the bit signal. Each subunit (14) also generates a portion of the data signal. Additionally each of the subunits (14) has a corresponding identity. Also included in the unit train (10) is a clock/data line (67) for relaying the clock signal and the data signal between the base unit (12) and each subunit (14).
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: January 14, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Stanley D. Harder, Richard A. Houghton, Richard H. Wallace