Abstract: Architectures, methods and systems are presented which combine a multiple of directories (e. g. L1 and L2 directory) into a single directory, while still allowing the individual levels to use their own organization which is best for overall performance. This integration is performed without compromising the organization at each level. With some small additions to the L2 directory, it is used simultaneously to perform both the L1 and L2 directory functions. Additionally, the same organizational structure allows the L2 array to serve both as a traditional L1 and simultaneous L2 array.

Abstract: Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.

Abstract: An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.

Abstract: A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits.

Abstract: A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits. The method further provides a way to bank the random access memory structures where data is stored.

Abstract: A method is provided for selecting a participant to issue. The method includes signaling a domino OR gate arbitration device upon a ready request of a participant having a priority, determining within the domino OR gate arbitration device the relative priority of the participant, signaling the domino OR gate arbitration device through an any-request device upon the ready request of a higher priority participant, and issuing the higher priority participant upon determining the higher priority participant to have a priority highest among participants ready for issue. The method includes gating one of a precharge signal and an evaluate signal of the precharged domino OR gate arbitration device by the ready request of the participant. The method further includes latching a result of the domino OR gate arbitration device and a clock signal, and gating the clock signal by the ready signal of the participant.

Abstract: An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.

Abstract: An interlocked pipelined CMOS (IPCMOS) family of logic circuits provides extremely high performance pipelined operation and guarantees error free operation where variations in timing are compensated for automatically by the circuits. The IPCMOS logic circuits also provide a standard interface that makes it possible to interface different macro types easily. The IPCMOS logic circuits feature interlocking in both the forward and reverse directions. This “handshaking” guarantees error free timing and makes it possible to eliminate the need for a global clock at the macro level. Timing signals are generated locally at the macro level from the handshaking signals between macros. This makes it possible for the local circuits to deal with global timing variations caused by power supply noise, ACLV, and parameter variations. The macros operate in a pipelined mode with data advancing automatically from macro to macro with the timing controlled by the local handshaking signals.

Abstract: A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO.sub.2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions.

Abstract: A DRAM for L2 cache is used in a computer memory hierarchy without compromising overall system performance. By proper organization and design, the DRAM L2 cache is many times larger than a SRAM implementation in the same technology, but without compromising overall system performance. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time. To achieve this, it is essential to minimize the total DRAM access time as much as possible by the use of early select techniques and pipelining.

Abstract: An optimized trench capacitor structure which is useful as a decoupling capacitor or a storage capacitor can be manufactured without added process complexity. As an on-chip decoupling trench capacitor structure, the structure reduces the series resistance to outer and inner plates and results in an acceptable RC delay, while maintaining a high capacitance per unit area. As a storage capacitor with a buried shield, the trench capacitor structure exhibits high immunity to alpha particle and cosmic radiation induced failures. The trench capacitor structure which includes a buried n-well in a silicon substrate. A trench is formed in the substrate and extends through the buried n-well. A dielectric film is formed on an inner surface of the trench, and an inner plate formed as a polysilicon fill within the trench is connected to a surface n+ film formed during definition of peripheral source/drain contacts of the integrated circuit.

Abstract: An integrated processor and level two (L2) dynamic random access memory (DRAM) are fabricated on a single chip. As an extension of this basic structure, the invention also contemplates multiprocessor "node" chips in which multiple processors are integrated on a single chip with L2 cache. By integrating the processor and L2 DRAM cache on a single chip, high on-chip bandwidth, reduced latency and higher performance are achieved. A multiprocessor system can be realized in which a plurality of processors with integrated L2 DRAM cache are connected in a loosely coupled multiprocessor system. Alternatively, the single chip technology can be used to implement a plurality of processors integrated on a single chip with an L2 DRAM cache which may be either private or shared. This approach overcomes a number of issues which limit the performance and cost of a memory hierarchy. When the L2 DRAM cache is placed on the same chip as the processor, the time needed for two chip-to-chip crossings is eliminated.

Abstract: An electronic computer memory system has first and second intermediate memory levels for use between a central processing unit and a main memory level. One or more buffer arrays have two sets of bus lines. A first set of buffer array bus lines communicates with associated bus lines of the first and second intermediate memory arrays. The second set of buffer array bus lines contains a number of bus lines less than the number of bus lines in the first memory array. By providing one or more buffers with two sets of bus lines, data can be transferred between the main memory level and the buffer or one intermediate memory level while data in the other intermediate memory level is operated on by a the central processing unit. By providing the buffer with one set of bus lines equal to the number of bus lines of the first and second intermediate memory arrays, high speed data transfer between the intermediate memory arrays can be achieved.

Abstract: An optimized trench capacitor structure which is useful as a decoupling capacitor or a storage capacitor can be manufactured without added process complexity. As an on-chip decoupling trench capacitor structure, the structure reduces the series resistance to outer and inner plates and results in an acceptable RC delay, while maintaining a high capacitance per unit area. As a storage capacitor with a buried shield, the trench capacitor structure exhibits high immunity to alpha particle and cosmic radiation induced failures. The trench capacitor structure which includes a buried n-well in a silicon substrate. A trench is formed in the substrate and extends through the buried n-well. A dielectric film is formed on an inner surface of the trench, and an inner plate formed as a polysilicon fill within the trench is connected to a surface n+ film formed during definition of peripheral source/drain contacts of the integrated circuit.

Abstract: A decoupling capacitor and protection circuit is provided that will assist the power supply network in stabilizing the voltage near circuits that demand short rapid transitions in electrical current. The protection circuit also significantly reduces the amount of electrical current drawn by defective large area decoupling capacitors. An inverter stage controls a switching circuit connected in series with a decoupling capacitor. A feedback circuit is provided from the output of the capacitor to the switching circuit. If the capacitor goes bad, then a voltage is present on the feedback circuit and the switching circuit ensures that the output of the failed capacitor is presented with an open circuit so that the short circuit current flow through the capacitor is eliminated. In this manner, the integrity of the other circuits located near the failed capacitor will operate appropriately.

Abstract: A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement.

Abstract: A two bit partitioning circuit for a dynamic programmed logic array which introduces two stages of delay in the signal path in one clock cycle, with minimum power dissipation. The circuit has two primary inputs and four outputs which serve as inputs to a bootstrap driver which produces an output signal to the programmed logic array. A basic path through the circuit consists of two stages, the first stage comprising two active devices (FET) and a first capacitive means, while the second stage comprises three active devices and a second capacitive means. The major portion of the capacitance of the second stage is provided by the capacitance of the bootstrap driver. The stages are dynamic with the discharge speed of the first stage being much faster than that of the second stage thereby enabling a signal to propagate through the two stages in one clock cycle, with the only power dissipation being that required to charge the two capacitive means.