Abstract: An arrangement to couple at least one I/O device to the main bus between a CPU and a main memory in a digital computer system is shown to include a random access memory made up of a dedicated part of the main memory and control circuitry to allow access between addresses in the random access memory and either the CPU or the at least one I/O device, such circuitry being arranged to give priority of access to the CPU except when data is actually being transferred from the I/O device and the random access memory.

Abstract: A multi-microprocessor apparatus utilizing a plurality of central processing units arranged in a parallel configuration. Each central processing unit which has its own local memory unit, communicates with a common memory unit on a time shared basis that is synchronized between each central processing unit and the common memory unit.

Abstract: A digital computer memory made up of a plurality of read only memory components arranged in a matrix of rows and columns. The outputs of the columns of memory components are connected to a voltage source and load resistors to provide the output terminals of the memory. Sets of digital words having at least a field or portion of a field with bits represented by the same logical state are grouped in such memory so that, when a word in such set is addressed, the bits in such field are produced at the output terminals by the volage source and load resistors. With such arrangement the number of read only memory components required in such memory is reduced.

Abstract: A microinstruction memory addressing control unit for a microprogram controlled digital computer is disclosed. The microinstruction memory stores an addressable fetch microprogram and independent sets of addressable microinstructions. Each one of the stored microinstructions in the sets thereof has an addressing control field. The microinstruction memory addressing control unit, in response to the microinstruction control field of a microinstruction currently under execution, is adapted to select as the next address for the memory one of a variety of addresses.

Abstract: An arrangement is shown for controlling transmission of blocks of information to and from a plurality of major components of a digital computer system interconnected by common buses. The disclosed arrangement operates so that any component of the system may normally seize, on a nonpriority basis, one of the buses at the beginning of any time slot defined by two successive clock pulses generated by a single source and applied to all components simultaneously; however, if a special instruction is encountered during execution of a program, any component may retain a bus for more than one time slot. The disclosed arrangement also permits error checking of transmitted information from a given major component without interfering with transmission from any other major component and automatically causes retransmission of any block of information found to be improperly transmitted originally.