Abstract: Ports including at least input and output signal lines are collected into port groups. For each port group three separate clock synchronized time division switches are connected respectively to the input signal lines, bus highways and the output signal lines. All time division switches of the system are synchronized by a system clock and each one is controlled by its own storage of selected addresses in time slot order. A plurality of bus highways is provided and the input time division switch connects signals to a specific bus highway of the system. A second time division switch selects the bus highway for connection to the output section of the port group. A third time division switch selects the output port to which the selected bus highway is connected. In one embodiment the bus highways directly connect the port groups. In another, a central inter-connect matrix is provided to make the connection between the first and second time division switches.

Abstract: Two data equipments are connected by switching equipment which supplies high speed lines for a modified data signal and a stuff control signal. A system clock or system clock derived signal is used in a stuffing pattern generator which generates a stuff control signal for one of the high speed lines. The stuffing pattern generator also controls the read terminal of a first buffer register receiving input data from a first equipment written into the register under the control of a clock generated from the system clock. The output from the first buffer register includes stuffing bits as well as data and the data and stuff signal is fed through a high speed line to a second buffer register. The write terminal of the second buffer register receives the stuff control signal to control input to the register and causes deletion of the stuff bits. The read terminal of the second buffer register is under control of the clock derived from the system clock to control the register output to the second equipment.