Abstract: The present invention provides mechanisms for removing duplicate signals during a communication session. More particularly an over-air signal is received at a given endpoint and a stream of electronic data is monitored at the same endpoint for a duplicate to the over-air signal. If a duplicate is detected in the electronic data stream, it is removed so that only one occurrence of the signal is received at the endpoint.

Abstract: A near field planar wavefront generation method that uses a relatively small number (three to five) of transmitting antennas disposed a predetermined distance from an antenna array having a multi-wavelength aperture that is part of a system under test. The method creates a synthesized one-dimensional linear planar wavefront of radiation over at least ten wavelengths for testing the antenna array of the system under test. The planar wavefront is formed at a specific frequency and at predetermined distance from the transmitting antennas, typically in the range of from 100 to 200 feet. The transmitting antennas synthesize a plane wave with linear phase progression to simulate tilt variations. To achieve this, electromagnetic energy signals emitted by the respective transmitting antennas are amplitude and phase weighted to synthesize the one dimensional linear plane wave to produce a combined wavefront having a linear phase front across the aperture of the antenna array of the system under test.

Abstract: A square root processing apparatus wherein an unknown number is sequentially squared and compared to a number whose square root is to be determined. The result of each comparison determines the state of a bit in the square root being determined. More specifically, the square root processor includes a Y register containing a number whose square root is to be determined, and an X register which is used to develop the square root of the contents of the Y register. The apparatus provides a means for initially setting the most significant bit stage of the X register to one, the remaining bit stages containing zeros. The contents of the X register are then squared by a high speed digital multiplier and compared with the contents of the Y register. If the squared number is greater than the contents of the Y register, the most significant bit stage of the X register is reset to zero. The apparatus then sets the next most significant bit stage of the X register to one and repeats the above-described sequence.

Abstract: Circuits are disclosed for normalizing a device which has a current-controlled frequency response, such as a YIG or a TWM device, to a predetermined current-frequency (I-F) characteristic in order that a device equipped with such a circuit can be preadjusted for substitution in a system for a like device without realigning the system. The normalizing circuit is in parallel with the device, and is comprised of a transistor and a compensating current-sensing resistor in series with the transistor. A shunt compensating current, I.sub.C, through the transistor is set by a voltage on a potentiometer to offset the I-F characteristic of the composite device and circuit from that of the device to a predetermined level and also by a feedback control circuit connected to the compensating current-sensing resistor. The slope of the offset characteristic is then adjusted to a predetermined value by adjusting the gain of a feedback control circuit between the transistor and a resistor which senses a voltage, V.sub.